Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-05-10
2002-07-16
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S602000, C438S618000, C438S637000
Reexamination Certificate
active
06420252
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to forming contacts on semiconductors and is particularly related to methods for forming self-aligned contacts on compound semiconductors.
BACKGROUND OF THE INVENTION
When metal contacts are formed on compound semiconductors, there is generally a need to provide a diffusion barrier between the contact metal and an active surface of the compound semiconductor. The diffusion barrier, which typically comprises materials such as platinum, tungsten, palladium and combinations or alloys thereof, is necessary to prevent contact and subsequent interaction between the contact metal and the semiconductor material. As is well known to those skilled in the art, interaction of the contact metal and the semiconductor material is highly undesirable. Such interaction may result in one or more elements of the compound semiconductor diffusing or intermixing with the contact metal, thereby altering the operational characteristics of the contact metal and semiconductor. Such interaction may degrade the crystalline structure of the semiconductor. Such interaction may also result in the formation of an alloy between the compound semiconductor and the contact metal, thereby changing the melting temperature of the semiconductor. In addition, the metal contacts formed on the semiconductor may not be as robust, and may be subject to more rapid and severe degradation under conditions of time and/or temperature than would otherwise occur with unmixed substances. Thus, barrier layers are typically provided to inhibit this reaction.
One prior art method for forming contacts on semiconductors is shown in
FIGS. 1A-1N
. Referring to
FIG. 1A
, a substrate
10
having a top surface
12
may comprise a dielectric or semiconductor material. A layer of a semiconductor material
14
is provided atop the first surface
12
of the substrate
10
, as shown in FIG.
1
B. Referring to
FIG. 1C
, a photoresist material
16
is then deposited atop the semiconductor layer. Referring to
FIG. 1D
, a photolithographic process may then be used to develop selected portions of the photoresist layer
16
. In
FIG. 1D
, photoresist layer
16
has first sections
18
A,
18
B,
18
C that are developed while second sections
20
A,
20
B remain undeveloped.
As shown in
FIG. 1E
, the developed portions of
18
A,
18
B,
18
C of photoresist layer
16
are removed, leaving behind the undeveloped portions
20
A,
20
B. The undeveloped portions
20
A,
20
B of photoresist layer overlie first sections
14
A,
14
B of the semiconductor layer
14
, while second sections
14
C,
14
D,
14
E of the semiconductor layer remain exposed. Referring to
FIG. 1F
, the second sections
14
C,
14
D,
14
E of the semiconductor layer are then removed, leaving behind semiconductor mesas
22
A,
22
B atop the first surface
12
of substrate
10
. As shown in
FIG. 1G
, the photoresist material is then stripped away to leave semiconductors exposed atop substrate
10
. Referring to
FIG. 1H
, a second photoresist layer
24
is then provided atop the semiconductor mesas
22
A,
22
B and the top surface
12
of substrate
10
. Referring to
FIG. 11
, the second photoresist layer
24
is then subjected to a photolithographic process to form openings
26
therein. The openings generally conform to a desired pattern for contacts or conductive traces.
Referring to
FIG. 1J
, a metal
28
is then deposited atop the structure. The metal
28
covers a top surface
30
of the second photoresist layer
24
and the portions of the semiconductor mesa
22
A,
22
B and substrate
10
exposed through the photoresist openings.
FIG. 1J-1
shows a magnified view of the metal
28
deposited atop one of the semiconductor mesas
22
shown in FIG.
1
J. Typically, when a contact
28
is formed atop a semiconductor device, the contact comprises a multi-layer structure. Each layer preferably comprises a conductive metal. In the structure shown in
FIG. 1J-1
, the contact
28
is formed by first depositing an adhesion metal
32
selected to form a bond with the semiconductor device. Next, a barrier metal
34
is deposited atop the adhesion metal. A contact metal, such as gold, silver, aluminum or copper, is then deposited atop the barrier metal. The barrier metal is designed to provide a diffusion barrier between the active surface of the semiconductor device and the contact metal deposited atop the barrier metal.
The various metal layers are provided by depositing metal particles atop the semiconductor. This is typically accomplished in a deposition tool such as by metal evaporation or by metal sputtering, wherein metal is deposited onto a semiconductor to build up a layer of a particular metal. The metal layers can have different thicknesses depending upon the required function of the device. For example, the contact metal layer
36
is typically thicker than the barrier metal layer. In addition, the thickness of each layer can be controlled by regulating the specific manufacturing techniques used when depositing the layers. As is generally known to those skilled in the art, the edges of later deposited, thicker metal layers tend to overlap the edges of earlier deposited, thinner metal layers. This is because the later deposited, thicker metal layer tends to spread over the edge of the earlier deposited, thinner layer. The overlapping edge of the later deposited layer is commonly referred to as a tail. As used herein, the term “tail” means the edge of the thicker metal layer that overlaps the edge of the thinner metal layer. As shown in
FIG. 1J-1
, the overlapping edge
38
of contact metal layer
36
extends beyond the edge
40
of barrier metal layer
34
to form tail
38
. As a result, the contact metal layer
36
is able to contact the active surface of semiconductor
22
, resulting in the contact metal-semiconductor interaction problems described above.
FIG. 1J-2
shows a magnified view of the edge of contact
28
formed atop semiconductor device
22
. As shown, the tail
38
of contact metal layer
36
is in direct contact with the active surface of semiconductor
22
. As a result, the contact metal
36
may interact with semiconductor
22
, causing the adverse problems described above.
One adverse consequence of contact metal-semiconductor interaction is shown in FIG.
1
K. When the elements comprising the compound semiconductor diffuse into the contact metal, an alloy
25
may form between the semiconductor
22
and the contact metal
36
. The formation of the alloy
25
is undesirable as it may adversely affect the mobility, the speed of switching, and/or the performance of the semiconductor. In certain embodiments, performance may suffer because the quality of the crystalline structure of the semiconductor is adversely affected. Diffusion may also alter the resistance of the semiconductor or the contact metal
36
, thereby changing the operating characteristics of the structure.
Referring to
FIGS. 1L and 1M
, after the contacts
28
have been formed atop the semiconductors
22
, a passivation layer
42
is provided atop the first surface
12
of the substrate
10
, and over the semiconductor mesas
22
and the contacts
28
deposited thereon. Referring to
FIG. 1N
, the passivation layer
42
is then selectively removed to form contact openings
44
that extend to the contact metal
28
.
Thus, there is a need for a method for forming robust contacts for compound semiconductors wherein the contact metal does not interact with the semiconductor. This may be accomplished by providing a barrier layer that effectively isolates the contact metal from the semiconductor.
SUMMARY OF THE INVENTION
In certain preferred embodiments of the present invention, a method of forming a self-aligned contact on a semiconductor includes forming a layer of a dielectric material, commonly referred to as a passivation layer, atop a semiconductor. The dielectric material layer preferably comprises an impervious, non-conductive material. Preferred dielectric materials for the passivation layer include glass, ceramic, silicon oxide, silic
Brown Michael G.
Douglas Edward W.
Koszi Louis A.
Schwed Stephen
Emcore Corporation
Lerner David Littenberg Krumholz & Mentlik LLP
Lytle Craig P.
Smith Matthew
LandOfFree
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