Methods of forming multilayer dielectric regions using...

Details Methods of forming multilayer dielectric regions using... Methods of forming multilayer dielectric regions using...

2001-05-16

2003-11-18

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S585000, C438S587000, C438S393000, C438S396000, C438S785000

Reexamination Certificate

active

06649502

ABSTRACT:

PRIORITY CLAIM
This application claims the benefit under 35 U.S.C. §119 of Korean Patent Application No. 2000-26083, filed on May 16, 2000, and Korean Patent Application No. 2002-13751, filed on Mar. 16, 2001, each of which is hereby incorporated by reference in its entirety.
FIELD OF THE INVENTION
The present invention relates to methods for forming dielectric regions for microelectronic devices, and more particularly, to methods for forming dielectric regions for devices such as memory cell capacitors.
BACKGROUND OF THE INVENTION
As semiconductor memory devices become increasingly integrated, the memory cells in such devices generally have become smaller. Thus, for example, areas for capacitors and transistors used in such memory cells have decreased. This decreased size can degrade storage capacity.
Accordingly, new capacitor structures have been introduced. Traditionally, storage capacitors commonly employed a stack structure but, in order to secure a sufficient capacity in a limited area, steric structures such as fin structures, cylinder structures and trench structures have been recently used. A capacitor having such a steric structure may have relatively large electrodes in comparison to those of a traditional stacked structure and, therefore, can have relatively larger storage capacitance.
Another technique for increasing storage capacitance of a capacitor is the use of a capacitor dielectric with increased dielectric constant, which can allow the size of dielectric region to be reduced. For example, recently developed devices include dielectrics formed of a metal oxide, such as tantalum oxide (Ta
2
O
5
) or aluminum oxide (Al
2
O
3
), or a ferroelectric material, such as material from a perovskite series, e.g., strontium titanate (ST) or barium strontium titanate (BST).
Tantalum oxide is larger in dielectric constant than silicon dioxide (SiO
2
) or silicon nitride (Si
3
N
4
). In particular, tantalum oxide has a dielectric constant of 24, while SiO
2
and Si
3
N
4
have dielectric constants of 3.9 and 7.8, respectively. Thus, a relatively thinner dielectric layer may be used in a capacitor with a tantalum oxide dielectric. However, a tantalum oxide layer also generally has a smaller energy band gap than a silicon oxide layer or a nitride oxide layer and, therefore, may exhibit a higher leakage current.
FIG. 1A
is a flow chart illustrating a process for manufacturing a conventional capacitor using a tantalum oxide dielectric layer. The tantalum oxide layer is formed through two deposition processes and two annealing processes. As shown in
FIG. 1A
, a lower capacitor electrode is formed on a semiconductor substrate (step
100
). The lower electrode is made of impurity-doped polycrystalline silicon. A first tantalum oxide layer is deposited on the lower capacitor electrode using a chemical vapor deposition (CVD) technique at a temperature of about 460° C. to 500° C. and a pressure of about 3.0 Torr to 5.0 Torr (step
102
). Preferably, the first tantalum oxide layer has a thickness of about 10 Å to about 50 Å. Thereafter, the first tantalum oxide layer undergoes a first annealing process in an ultraviolet-ozone atmosphere (step
104
). Subsequently, a second tantalum oxide layer is deposited in a thickness of about 50 Å to about 100 Å under the same deposition atmosphere as the first tantalum oxide layer (step
106
). Thereafter, the second tantalum oxide layer undergoes a second annealing process in an ultraviolet-ozone atmosphere (step
108
). Finally, an upper capacitor electrode is deposited on the second tantalum oxide layer (step
110
). The deposition process of the first tantalum oxide layer, the first annealing process, the deposition process of the second tantalum oxide layer and the second annealing process can be performed in-situ.
FIG. 1B
is a graph illustrating process time with respect to temperature and pressure for a capacitor fabrication process. The vertical axis denotes temperature or pressure, and the horizontal axis denotes a time period. As shown in
FIG. 1B
, when first and second tantalum oxide layers are deposited as described above, a time period required for depositing the first tantalum oxide layer is 214 seconds, and a time period for depositing the second tantalum oxide layer is 239 seconds. Time for each of the first and second annealing processes is 200 seconds.
When a lower capacitor electrode of a capacitor is made of a metal, such as titanium nitride (TiN), ruthenium (Ru) or platinum (Pt), the storage capacitance of a capacitor may significantly increase in comparison to a capacitor using a polycrystalline silicon layer as a lower capacitor electrode. However, when the lower capacitor electrode is made of a metal, such as ruthenium, step coverage characteristics of a tantalum oxide layer may greatly depend on deposition pressure and/or deposition temperature. For example, when a tantalum oxide layer is deposited on a polycrystalline silicon layer at a pressure of 0.1 Torr to several Torr using a low-pressure chemical vapor deposition (LPCVD) technique, variation of a step coverage of the tantalum oxide layer with deposition pressure may be very small. However, when a tantalum oxide layer is deposited on a metal layer, such as a ruthenium layer, increased deposition pressure tends to deteriorate step coverage of the tantalum oxide layer. This is because a sticking coefficient between the capacitor lower electrode and the tantalum oxide layer differs depending on the material composition of the lower capacitor electrode. Therefore, in order to use a metal layer, such as a ruthenium layer, as a capacitor lower electrode, it is desirable to deposit a tantalum oxide dielectric layer on the metal layer at a sufficiently low temperature and a sufficiently low pressure to prevent deterioration of step coverage of the tantalum oxide layer. However, due to a low deposition pressure, this can reduce manufacturing throughput.
FIG. 9A
is a cross-sectional view illustrating a metal layer formed on a metal oxide layer (i.e., tantalum oxide layer) according to a conventional process. A ruthenium layer
91
is deposited on a semiconductor substrate
90
to a predetermined thickness. Thereafter, a tantalum oxide layer is formed on the ruthenium layer
91
such that first and second deposition layers
92
-
1
, layers
92
-
2
made of Ta
2
O
5
are sequentially deposited.
However, when the first tantalum oxide layer layers
92
-
1
is deposited at a high temperature and in a high pressure, step coverage of the ruthenium layer
91
may be deteriorated. This can also decrease step coverage of the second tantalum oxide layer layers
92
-
1
. This is because the initial deposition layer layers
92
-
1
may have a relatively large sticking coefficient and may be deposited such that impurities, such as carbon, are not satisfactorily decomposed. Deposition at lower temperature and lower pressure could be performed to improve a step coverage of the tantalum oxide layer. However, low temperature and pressure may reduce deposition rate (i.e., deposition speed) of the tantalum oxide layer, leading to a low manufacturing throughput.
For the foregoing reasons, there is a need for a method of depositing a metal oxide layer of a semiconductor capacitor that can improve both a step coverage and a manufacturing throughput.
SUMMARY OF THE INVENTION
According to some embodiments of the present invention, a dielectric region, such as a dielectric region for a storage capacitor of a memory cell, is fabricated by depositing tantalum oxide on a substrate to a thickness of about 1 Å or greater in an atmosphere having a temperature in a range from about 350° C. to about 460° C. and a pressure in a range from about 0.01 Torr to about 2.0 Torr to form a first tantalum oxide layer. Tantalum oxide is subsequently deposited on the first tantalum oxide layer to a thickness of about 30 Å or greater in an atmosphere having a temperature in a range from about 400° C. to about 500° C. and a pressure in a range from about 0.1 Torr to about 10.0 Tor

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