Methods of forming integrated circuitry and integrated circuitry

Details Methods of forming integrated circuitry and integrated circuitry Methods of forming integrated circuitry and integrated circuitry

1998-06-09

1999-08-17

Powell, William

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Junction field effect transistor

257287, 438719, 438735, 438753, 216 2, H01L 2980, H01L 31112

Patent

active

059397411

ABSTRACT:
In one aspect, a plurality of layers are formed over a substrate and a series of first trenches are etched into a first of the layers in a first direction. A series of second trenches are etched into the first layer in a second direction which is different from the first direction. Collectively, the first and second trenches define a plurality of different substrate elevations with adjacent elevations being joined by sidewalls which extend therebetween. Sidewall spacers are formed over the sidewalls, and material of the first layer is substantially selectively etched relative to material from which the spacers are formed. Material comprising the spacer material is substantially selectively etched relative to the first material. In a preferred implementation, the etching provides a plurality of cells which are separated from one another by no more than a lateral width dimension of a previously-formed spacer.

REFERENCES:
patent: 3579057 (1971-05-01), Stoller
patent: 5013680 (1991-05-01), Lowrey et al.
patent: 5628917 (1997-05-01), MacDonald
patent: 5660680 (1997-08-01), Keller

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