Methods of forming integrated circuit capacitors including etch

Details Methods of forming integrated circuit capacitors including etch Methods of forming integrated circuit capacitors including etch

1997-10-09

1998-07-28

Nguyen, Tuan H.

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438 3, 438253, 438240, H01L 2120

Patent

active

057862591

ABSTRACT:
A method of forming a capacitor for an integrated circuit device includes the step of forming a first conductive layer on an integrated circuit substrate wherein the first conductive layer covers a portion of the integrated circuit substrate and wherein a second portion of the integrated circuit substrate is exposed. An etch stopping layer is formed on the first conductive layer, and an insulating layer is formed on the etch stopping layer and on the exposed portion of the integrated circuit substrate. The insulating layer is etched using the etch stopping layer as an etching endpoint so that a portion of the insulating layer on the second portion of the integrated circuit substrate remains adjacent the first conductive layer and so that the etch stopping layer is exposed. The etch stopping layer is removed and a dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the dielectric layer opposite the first conductive layer so that the first conductive layer defines a lower capacitor electrode and the second conductive layer defines an upper capacitor electrode.

REFERENCES:
patent: 5366920 (1994-11-01), Yamamichi et al.
patent: 5416042 (1995-05-01), Beach et al.
patent: 5478772 (1995-12-01), Fazan
patent: 5506166 (1996-04-01), Sandhu et al.
patent: 5670410 (1997-09-01), Pan
Kuniaki Koyama et al., A Stacked Capacitor With (Ba.sub.x Sr.sub.1-x)TiO.sub.3 For 256M DRAM, IEDM, 1991, 823-826.

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