Methods of forming integrated circuit capacitors having...

Details Methods of forming integrated circuit capacitors having... Methods of forming integrated circuit capacitors having...

1999-04-09

2001-04-10

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S253000

Reexamination Certificate

active

06214688

ABSTRACT:

RELATED APPLICATION
This application is related to Korean Appn. No. 98-12563, filed Apr. 9, 1998, the disclosure of which is hereby incorporated herein by reference.
1. Field of the Invention
The present invention relates to methods of forming integrated circuit devices and, more particularly, to methods of forming integrated circuit capacitors.
2. Background of the Invention
As DRAMs increase in memory cell density, there is a continuous challenge to maintain sufficiently high storage capacitance within memory cells despite decreasing cell area. Additionally there is a continuing goal to further decrease cell area. Many methods have been proposed to keep the capacitance of such storage capacitors at acceptable levels. One approach is to increase the height of the storage node (electrode of the capacitor). Another approach is to use high dielectric materials such as Ta
2
O
5
, or BST.
However, there are some problems with the approach to increasing the height of the storage node. For example, if the required height of the storage node is more than 10,000 Å, it becomes very difficult to pattern conductive layers as storage nodes. There are also some problems with using high dielectric materials, such as Ta
2
O
5
and BST, as dielectric films. These problems include the complexity of the fabrication process and reduced reliability.
Attempts have been made to address these problems. For example,
FIG. 1A
shows, in cross-section, a “one cylinder stack” (OCS) structure of a capacitor storage node according to the prior art. As can be seen in
FIG. 1A
, the cup-shaped storage node has a capacitance of about two times larger than that of a simple stack capacitor structure because both outer and inner surfaces of the node can be utilized as an effective capacitor area.
FIG. 1B
shows, in cross-section, a simple stacked capacitor with an HSG layer on its surface according to the prior art. The simple stacked capacitor with an HSG layer has a capacitance about two times larger than that of a simple stacked capacitor without an HSG layer. One cylinder stack capacitors with HSG layers on both inner and outer surface also can be formed.
FIGS. 2A-2D
are cross-sectional diagrams which illustrate a method of fabricating an OCS capacitor with an HSG layer thereon. Referring now to
FIG. 2A
, a device isolating layer
12
is formed on a predetermined region of a semiconductor substrate
10
to define active and inactive regions. A gate electrode structure
14
is formed over the semiconductor substrate
10
. A gate oxide layer also is disposed between the gate electrode structure
14
and the substrate
10
. Source/drain regions
16
are formed in the active region adjacent to the gate electrode layer. An interlayer insulating layer
18
is formed over the semiconductor substrate
10
and the gate electrode structure
14
. A contact hole
19
is opened in the interlayer insulating layer
18
to expose one of the source/drain regions
16
. A polysilicon layer
20
is used as a storage node. This layer is deposited in the contact hole
19
and over the insulating layer
18
. A photoresist layer pattern
22
is formed over the polysilicon layer
20
to define a storage node region. A low temperature oxide layer
24
is deposited over the polysilicon layer
20
(including the photoresist pattern
22
) to a thickness of about 2,500 Å.
Referring to
FIG. 2B
, the low temperature oxide layer
24
is then dry etched to form sidewall spacers
24
a
on the lateral edges of the photoresist pattern
22
. Using the photoresist pattern
22
and the sidewall spacers
24
a as a mask, a timed etching step is performed on the insulating layer
20
to remove more than half of the original thickness thereof.
The formation of the storage node structure is next addressed and illustrated in
FIGS. 2C-2D
. After removing the photoresist pattern
22
, the polysilicon layer
20
is etched back, using the sidewall spacers
24
a
as a mask, to form the storage node structure
20
a
, as shown in FIG.
2
D. Subsequently, an HSG layer (not shown) is formed on the surfaces of the storage node
20
a
. A dielectric film and top plate are then formed on the storage node
20
a
using conventional techniques.
The above-described method has some drawbacks. For example, the timed etch conducted on the insulating layer may not provide process reliability, and the polymer resulting from the etch back may contaminate the storage node which affects the dielectric characteristics. The etch back using the sidewall spacers as a mask also may cause a variation in storage node thickness. Moreover, since the thickness of the top portion of the storage node is less than 1,000 Å, the storage node may fall down during a cleaning process and the HSG formation thereon may totally consume the storage node and cause it to break off.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved methods of forming integrated circuit capacitors and capacitors formed thereby.
It is another object of the present invention to provide methods of forming integrated circuit capacitors having high capacitance and capacitors formed thereby.
These and other objects, features and advantages of the present invention are provided by methods of forming integrated circuit capacitors that include the steps of forming a first electrically insulating layer having a conductive plug therein, on a semiconductor substrate, and then forming second and third electrically insulating layers of different materials on the first electrically insulating layer. A contact hole is then formed to extend through the second and third electrically insulating layers and expose the conductive plug. Next, a conductive layer is formed in the contact hole and on the third electrically insulating layer. A step is then performed to planarize the conductive layer to define a U-shaped electrode in the contact hole. The third electrically insulating layer is then etched-back to expose upper portions of outer sidewalls of the U-shaped electrode, using the second electrically insulating layer as an etch stop layer. However, the second electrically insulating layer is not removed but is left to act as a supporting layer for the U-shaped electrode. This second electrically insulating layer preferably comprises a composite of a nitride layer and an oxide layer. To increase the effective surface area of the U-shaped electrode, an HSG layer may also be formed on the inner and outer sidewalls of the U-shaped electrode. According to another aspect of the present invention, the planarization step may be preceded by the step of forming a fourth electrically insulating layer on the conductive layer. In this case, the planarization step will include the step of planarizing the fourth electrically insulating layer and the conductive layer to define a U-shaped electrode in the contact hole. To complete the capacitor, steps may also be performed to form a capacitor dielectric layer on the U-shaped electrode and on the second electrically insulating layer and then form an upper capacitor electrode on the capacitor dielectric layer.


REFERENCES:
patent: 5956587 (1999-09-01), Chen et al.
patent: 6077742 (1999-09-01), Chen et al.
patent: 198 60 052 A1 (1999-10-01), None
patent: 99-297960 (1999-10-01), None

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