Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to nonconductive state
Reexamination Certificate
2005-05-20
2010-02-16
Nguyen, Cuong Q (Department: 2811)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to nonconductive state
C438S281000, C438S215000, C438S333000, C438S467000, C438S601000
Reexamination Certificate
active
07662674
ABSTRACT:
Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a metallic fuse structure by forming at least one via on a first interconnect structure, lining the at least one via with a barrier layer, and then forming a second interconnect structure on the at least one via.
REFERENCES:
patent: 6111301 (2000-08-01), Stamper
patent: 7298639 (2007-11-01), Hsu et al.
patent: 2004/0262768 (2004-12-01), Cho et al.
patent: 2005/0001241 (2005-01-01), Doyle
Bohr Mark
He Jun
Maiz Jose A.
Intel Corporation
Nguyen Cuong Q
Ortiz Kathy J.
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