Methods of forming conductive polysilicon lines and bottom gated

Details Methods of forming conductive polysilicon lines and bottom gated Methods of forming conductive polysilicon lines and bottom gated

1995-12-04

1997-08-19

Bowers, Jr., Charles L.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

438596, 438655, H01L 2184

Patent

active

056588070

ABSTRACT:
A semiconductor processing method of forming a conductive polysilicon line relative to a substrate includes, a) providing a line of silicon on a substrate, the line having an outer top surface and outwardly exposed opposing outer sidewall surfaces, the line ultimately comprising conductively doped polysilicon; b) masking the line outer top surface with a masking material; c) with the masking material in place, depositing a metal layer atop the substrate and over the masking material and the outwardly exposed line outer sidewall surfaces; d) annealing the line to impart a silicidation reaction between the metal and opposing silicon sidewalls to form opposing metal silicide runners extending along the line sidewalls, the masking material preventing a silicidation reaction from occurring between the metal and line outer top surface; and e) stripping the metal layer from atop the line. Such a line is preferably used as a bottom gate for a thin film transistor. The invention also includes conductive polysilicon lines and thin film transistors.

REFERENCES:
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Translation of JP 60-37124 cited previously.
S. Wolf & R.N. Tauber, "Silicon Processing for the VLSI ERA" vol I, Jun. 1986 pp. 397-399, 179-180.
S. Wolf, "Silicon Processing for the VLSI ERA" vol. II, Jun. 1992, pp. 144-147, 150-152, 358-359.

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