Methods of forming a local interconnect and a high resistor poly

Details Methods of forming a local interconnect and a high resistor poly Methods of forming a local interconnect and a high resistor poly

1992-06-25

1993-11-30

Hearn, Brian E.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

437200, 437918, 148DIG106, H01L 21312

Patent

active

052661563

ABSTRACT:
Methods of forming local interconnects and high resistor polysilicon loads are disclosed. The local interconnects are formed by depositing a layer of polysilicon over CoSi.sub.2 in partially fabricated semiconductor wafers. The polysilicon is then coated with cobalt and annealed to form a second layer of of CoSi.sub.2. The method can be expanded to form a high resistor polysilicon load by depositing and patterning an oxide layer to form contact windows before application of the polysilicon layer. Another oxide layer is deposited over the polysilicon and patterned before application of the cobalt layer to define the areas which create the resistor load.

REFERENCES:
patent: 4657628 (1987-04-01), Holloway et al.
patent: 4676866 (1987-06-01), Tang et al.
patent: 4912061 (1990-03-01), Nasr
patent: 4968645 (1990-11-01), Baldi et al.
patent: 4980020 (1990-12-01), Douglas
patent: 5010032 (1991-04-01), Tang et al.
patent: 5126279 (1992-06-01), Roberts
A New Device Interconnect Scheme for Sub-Micron VLSI by Devereaux C. Chen, et al., 118, IEDM (1984).
VLSI Local Interconnect Level Using Titanium Nitride by Thomas Tang, et al., 590, IEDM (1985).

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