Methods of formation of a silicon nanostructure, a silicon...

Details Methods of formation of a silicon nanostructure, a silicon... Methods of formation of a silicon nanostructure, a silicon...

2000-03-14

2001-08-14

Nguyen, Nam (Department: 1753)

Chemistry: electrical and wave energy

Processes and products

Coating, forming or etching by sputtering

C204S192230

Reexamination Certificate

active

06274007

ABSTRACT:

The invention relates to methods of forming quasi-one-dimensional solid-state silicon nanostructures. Such nanostructures may form the basis for nanoscale electronic and optoelectronic fabrication techniques, particularly but not exclusively of silicon quantum wire arrays, and can be used to fabricate silicon-based optoelectronic and nanoelectronic devices.
More particularly, the invention concerns forming silicon quantum wires by ion irradiation and, more specifically, to a process of sputtering a high-purity surface of silicon-on-insulator (SOI) material by a uniform flow of nitrogen molecular ions, so as to form a wave-like relief providing an array of nanoscale silicon “quantum wires”. The quantum wire array can be used as a light source in optoelectronic devices through the array conduction or in nanoelectronic devices; e.g. as a channel in a field effect transistor (FET).
A known method for forming silicon quantum wires with a cross-section of 10×15 nm
2
embedded in silicon oxide uses low-energy ion implantation of oxygen into silicon, electron-beam lithography and wet chemical etching, followed by high-temperature annealing in an inert environment. This results in the formation of silicon quantum wires embedded in silicon oxide at the bottom centre of V-grooves (Y. Ishikawa, N. Shibata, F. Fukatsu “Fabrication of [110]-aligned Si quantum wires embedded in SiO
2
by low-energy oxygen implantation” Nuclear Instruments and Methods in Physics Research, B, 1999, v. 147, pp. 304-309, Elsevier Science Ltd.) [Ref
1
].
There are several disadvantages to this known method. The use of electron-beam lithography and wet chemical etching when forming V-grooves on the silicon surface both limit the element density of the structure and reduce the wire yield. The absence of in situ control of the process further reduces the wire yield. The small wire density prevents the wires being useful for nanoelectronic devices of the type in which the interaction of charged particles in the neighbouring wires is important.
Previously published work, of which the present inventors were among the joint authors, discloses a method of forming wave-ordered-structures (WOS) on silicon, and in particular on SOI. The method comprises the steps of sputtering the SOI silicon layer by a nitrogen molecular ion probe scanned in a raster pattern in an ultra-high vacuum so as to form a periodical, wave-like nanoscale relief (WOS). The “wave front” of the nanoscale relief is in the direction of the ion incidence. The method includes detecting a secondary ion emission signal from the SOI insulator and terminating sputtering when this signal reaches a predetermined value. This reference also discloses the dependence of WOS formation upon the ion energy, E, the ion incidence angle, &thgr;, relative to the surface normal, and the temperature, T, of the SOI sample. The work also identifies a characteristic of the relief formation process, namely the sputtering depth D
m
corresponding to the onset of intense growth of a WOS and discusses the dependency of D
m
upon E, &thgr;, T, and the WOS wavelength &lgr;. The work further indicates that the SOI silicon thickness D
B
should not be less than the sputtering depth at which a stable WOS is formed with the desired wavelength (this depth being equal to the relief formation depth referred to hereinafter as D
F
). (V. K. Smirnov, D. S. Kibalov, S. A. Krivelevich, P. A. Lepshin, E. V. Potapov, R. A. Yankov, W. Skorupa, V. V. Makarov, A. B. Danilin “Wave-ordered structures formed on SOI wafers by reactive ion beams”—Nuclear Instruments and Methods in Physics Research B, 1999, v. 147, pp. 310-315, Elsevier Science Ltd.) [Ref
2
].
Further work involving one of the present inventors discloses a process of annealing material of the type disclosed in Ref
2
in an inert environment at a temperature of 1000° C. for one hour and the resulting internal structure of a WOS at the silicon-insulator interface of the SOI material. (V. K. Smirnov, A. B. Danilin; “Nanoscale wave-ordered structures on SOI”—Proceedings of the NATO Advanced Research Workshop “Perspective, science and technologies for novel silicon on insulator devices”/Ed By P. I. F. Hemment, 1999, Elsevier Science Ltd.) [Ref
3
].
Further work involving one of the present inventors discloses the dependencies of silicon nitride (Si
3
N
4
) layer thickness, D
N
, on the ion energy E, ion incidence angle to the surface and high-temperature annealing (900-1100° C. for one hour). The annealing has no effect on D
N
but maximises the Si/Si
3
N
4
interface sharpness. As shown therein, D
N
is equal to the ion penetration range into silicon, R, which is shown to be a linear function of E for the same energy range as that used for WOS formation. On the basis of data disclosed in this reference, the dependence of R on E can be expressed as:
R(nm)=1.5E(keV)+4.  (1)
(V. I. Bachurin, A. B. Churilov, E. V. Potapov, V. K. Smirnov, V. V. Makarov and A. B. Danilin; “Formation of Thin Silicon Nitride Layers on Si by Low Energy N
2
+
Ion Bomardment”—Nuclear Instruments and Methods in Physics Research B, 1999, v. 147, pp. 316-319, Elsevier Science Ltd.) [Ref
4
].
The above mentioned references Ref
2
, Ref
3
and Ref
4
in combination disclose a basic method for the formation of a silicon quantum wire array. The principal advantage of using a silicon quantum wire array, as compared with the use of separated wires, in nanoelectronic and optoelectronic devices lies firstly in the increase of device yield and enhancement of the signal-to-noise ratio of the current characteristics, and also in providing the potential for new capabilities in array-based devices due to the interaction of charged particles in neighbouring quantum wires.
There are a number of disadvantages associated with the basic method as disclosed in Ref
2
, Ref
3
and Ref
4
. Ref
2
does not address the question of whether the WOS wavelength &lgr; changes as the sputtering depth increases from D
m
to D
F
or whether there is any inter-relationship between D
m
and D
F
. The present invention recognises that the characteristics of the process should be related to the final WOS structure as developed at the depth D
F
rather than to the depth D
m
as discussed in Ref
2
. In addition, Ref
2
does not address the question of whether there are limits of the domain in the (E, &thgr;) plane in which WOS formation takes place.
Such limitations in the work disclosed in Ref
2
, Ref
3
and Ref
4
mean that the required thickness of the SOI silicon layer cannot generally be predetermined from the relationships between the various parameters as discussed in these references. In addition, the essential parameters for controlling the sputtering process (ion energy E, ion incidence angle &thgr; and SOI temperature T) cannot be predetermined. Further, for the isolation of neighbouring silicon wires in the WOS formed in SOI, it is important to ensure the troughs of the WOS relief coincide accurately with the border between the SOI silicon layer and the SOI insulator layer. Ref
2
discloses that the secondary ion emission signal may be employed as a basis for terminating the sputtering process, but does not disclose any way of pre-determining a value of the signal which corresponds to isolation of the silicon wires.
That is, the previously published work does not disclose a general method allowing a WOS to be formed reliably such that the troughs of the WOS coincide with the SOI silicon-insulator border so as to form an array of isolated silicon wires.
In addition, for practical purposes in applying such a process by integration with silicon-based nanoelectronic and optoelectronic technology, it is necessary to ensure the formation of the nanostructure array on a specified microarea of the surface in order to obtain a useful structure, for example, in the form of two isolated silicon pads connected by the array.
However, the previously published work does not address such issues as whether techniques such as lithogra

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