Methods of fabrication of semiconductor dice having back...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S639000, C438S672000

Reexamination Certificate

active

06962867

ABSTRACT:
An apparatus and method of rerouting redistribution lines from an active surface of a semiconductor substrate to a back surface thereof and assembling and packaging individual and multiple semiconductor dice with such rerouted redistribution lines formed thereon. The semiconductor substrate includes one or more vias having conductive material formed therein and which extend from an active surface to a back surface of the semiconductor substrate. The redistribution lines are patterned on the back surface of the semiconductor substrate, extending from the conductive material in the vias to predetermined locations on the back surface of the semiconductor substrate that correspond with an interconnect pattern of another substrate for interconnection thereto.

REFERENCES:
patent: 3648131 (1972-03-01), Stuby
patent: 3761782 (1973-09-01), Youmans
patent: 4833521 (1989-05-01), Early
patent: 5386142 (1995-01-01), Kurtz et al.
patent: 5455445 (1995-10-01), Kurtz et al.
patent: 5762744 (1998-06-01), Shibata et al.
patent: 5872051 (1999-02-01), Fallon et al.
patent: 5950304 (1999-09-01), Khandros et al.
patent: 5973396 (1999-10-01), Farnworth
patent: 5994766 (1999-11-01), Shenoy et al.
patent: 6011314 (2000-01-01), Leibovitz et al.
patent: 6018196 (2000-01-01), Noddin
patent: 6020220 (2000-02-01), Gilleo et al.
patent: 6025647 (2000-02-01), Shenoy et al.
patent: 6048753 (2000-04-01), Farnworth et al.
patent: 6166444 (2000-12-01), Hsuan et al.
patent: 6168969 (2001-01-01), Farnworth
patent: 6225143 (2001-05-01), Rao et al.
patent: 6261375 (2001-07-01), Siniaguine et al.
patent: 6287976 (2001-09-01), Siniaguine et al.
patent: 6322903 (2001-11-01), Siniaguine et al.
patent: 6323134 (2001-11-01), Siniaguine
patent: 6429096 (2002-08-01), Yanagida
patent: 2002/0125566 (2002-09-01), Tonami et al.
patent: 2003/0003724 (2003-01-01), Uchiyama et al.
patent: 09-321175 (1997-12-01), None
Advertisement, “Laser Micromachining,” MicroConnex Systems, 34935 SE Douglas Street, Snoqualmie, WA 98065.
Advertisement, “ESI 520 Drilling Station,” MicroConnex Systems, 34935 SE Douglas Street, Snoqualmie, WA 98065.
Advertisement, “Damage Free Thinning,” Tru-Si Technologies, 657 North Pastoria Ave., Sunnyvale, CA 94085.
Advertisement, “Through-Silicon Vias,” Tru-Si Technologies, 657 North Pastoria Ave., Sunnyvale, CA 94085.
Advertisement, “TE-2001-M,” Tru-Si Technologies, 657 North Pastoria Ave., Sunnyvale, CA 94085.
Advetisement, “TE-2001-UT,” Tru-Si Technologies, 657 North Pastoria Ave., Sunnyvale, CA 94085.
http://www.trusi.com/article9.htm, Savastiouk, Sergey, “New Process Forms Die Interconnects by Vertical Wafer Stacking,” pps. 1-2,chipScale Review.
http://www.trusi.com/article7.htm, Savastiouk, Sergey, “Moore's Law—the z dimension,” pps. 1-3,Solid State Technology.
http://www.trusi.com/articlefchip1.htm, Francis, David, “Thinning Wafers For Flip Chip Applications,” pps. 1-8,High Density Interconnect.
http://www.trusi.com/articlesb2.htm, Savastiouk et al., “Thinner packages vital for third-dimensional expansion,” pps. 1-6,The Next Dimension, Advanced Packaging, Sep./Oct. 1998.
http://www.trusi.com/articles2.htm, Savastiouk, Sergey, “A new start-up promises to revelutionize wafer thinning and boost chip packaging density,” pps. 1-3,Semiconductor European, Aug. 1998.
http://www.trusi.com/articlese1.htm, Savastiouk, Sergey, “Atomospheric Downstream Plasma-An Approach to 300-mm Wafer Thinning, Semi Global 300mm Report,” pps. 1-4,Semi Global300mm Report, Jul. 1998.
http://www.trusi.com/articlesf1.htm, Savastiouk et al., “Atmospheric downstream plasma—a new tool for semiconductor processing,” pps. 1-6,Solid State Technology, Jul. 1998.
http://www.trusi.com/oleg1.htm, Siniaguine, Oleg, “Atmospheric Downstream Plasma Etching of Si Wafers,” pps. 1-9.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Methods of fabrication of semiconductor dice having back... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods of fabrication of semiconductor dice having back..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of fabrication of semiconductor dice having back... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3496958

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.