Methods of fabricating silicon carbide power devices by...

Details Methods of fabricating silicon carbide power devices by... Methods of fabricating silicon carbide power devices by...

1999-11-30

2001-10-16

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ion implantation of dopant into semiconductor region

C438S522000, C438S965000

Reexamination Certificate

active

06303475

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to methods of fabricating power devices, and more particularly to methods of fabricating silicon carbide power devices.
BACKGROUND OF THE INVENTION
Power devices are widely used to carry large currents and support high voltages. Modem power devices are generally fabricated from monocrystalline silicon semiconductor material. One widely used power device is the power Metal Oxide Semiconductor Field Effect Transistor (MOSFET). In a power MOSFET, a control signal is supplied to a gate electrode that is separated from the semiconductor surface by an intervening insulator, which may be, but is not limited to, silicon dioxide. Current conduction occurs via transport of majority carriers, without the presence of minority carrier injection that is used in bipolar transistor operation. Power MOSFETs can provide an excellent safe operating area, and can be paralleled in a unit cell structure.
As is well known to those having skill in the art, power MOSFETs may include a lateral structure or a vertical structure. In a lateral structure, the drain, gate and source terminals are on the same surface of a substrate. In contrast, in a vertical structure, the source and drain are on opposite surfaces of the substrate.
One widely used silicon power MOSFET is the double diffused MOSFET (DMOSFET) which is fabricated using a double-diffusion process. In these devices, a p-base region and an n+ source region are diffused through a common opening in a mask. The p-base region is driven in deeper than the n+ source. The difference in the lateral diffusion between the p-base and n+ source regions forms a surface channel region. An overview of power MOSFETs including DMOSFETs may be found in the textbook entitled
“Power Semiconductor Devices”
by B. J. Baliga, published by PWS Publishing Company, 1996, and specifically in Chapter 7, entitled “Power MOSFET”, the disclosure of which is hereby incorporated herein by reference.
Recent development efforts in power devices have also included investigation of the use of silicon carbide (SiC) devices for power devices. Silicon carbide has a wide bandgap, a high melting point, a low dielectric constant, a high breakdown field strength, a high thermal conductivity, and a high saturation electron drift velocity compared to silicon. These characteristics may allow silicon carbide power devices to operate at higher temperatures, higher power levels and with lower specific on-resistance than conventional silicon-based power devices. A theoretical analysis of the superiority of silicon carbide devices over silicon devices is found in a publication by Bhatnagar et al. entitled “Comparison of 6H-SiC, 3C-SiC and Si for Power Devices”, IEEE Transactions on Electron Devices, Vol. 40, 1993, pp. 645-655. A power MOSFET fabricated in silicon carbide is described in U.S. Pat. No. 5,506,421 to Palmour entitled “Power MOSFET in Silicon Carbide” and assigned to the assignee of the present invention.
Notwithstanding these potential advantages, it may be difficult to fabricate power devices including power MOSFETs in silicon carbide. For example, as described above, the double-diffused MOSFET (DMOSFET) is generally fabricated in silicon using a double diffusion process wherein the p-base region is driven in deeper than the n+ source. Unfortunately, in silicon carbide, the diffusion coefficients of conventional p- and n-type dopants are small compared to silicon, so that it may be difficult to obtain the required depths of the p-base and n+ source regions using acceptable diffusion times and temperatures. Ion implantation may also be used to implant the p-base and the n+ source. See, for example, “High-Voltage Double-Implanted Power MOSFET's in 6H-SiC” by Shenoy et al., IEEE Electron Device Letters, Vol. 18, No. 3, March 1997, pp. 93-95. However, it may be difficult to control the depth and lateral extent of ion implanted regions. Moreover, the need to form a surface channel surrounding the source region may require the use of two separate implantation masks. It may then be difficult to align the p-base and the source regions to one another, thereby potentially impacting the device performance.
Published PCT International Application WO 98/02916, published Jan. 22, 1998, describes a method for producing a doped p-type channel region layer having on laterally opposite sides thereof doped n-type regions in a silicon carbide layer for producing a voltage-controlled semiconductor device. A masking layer is applied on top of a silicon carbide layer that is lightly n-doped. An aperture is etched in the masking layer extending to the silicon carbide layer. N-type dopants are implanted into an area of the silicon carbide layer defined by the aperture for obtaining a high doping concentration of n-type in the surface-near layer of the silicon carbide layer under the area. P-type dopants having a considerably higher diffusion rate in silicon carbide than the n-type dopants, are implanted into an area of the silicon carbide layer defined by the aperture to such a degree that the doping type of the surface-near layer is maintained. The silicon carbide layer is then heated at such a temperature that the p-type dopants implanted in the surface-near layer diffuse into the surrounding regions of the silicon carbide layer that is lightly n-doped, to such a degree that a channel region layer in which p-type dopants dominates is created laterally to the highly doped n-type surface-near layer and between this layer and lightly n-doped regions of the silicon carbide layer. As described in this International Application, the heating is carried out a temperature above 1650° C. and below 1800°.
SUMMARY OF THE INVENTION
The present invention provides methods of fabricating silicon carbide power devices by masking the surface of a silicon carbide substrate to define an opening at the substrate, implanting p-type dopants into the silicon carbide substrate through the opening at implant energy and dosage that form a deep p-type implant, and implanting n-type dopants into the silicon carbide substrate through the opening at implant energy and dosage that form a shallow n-type implant relative to the deep p-type implant. According to the invention, the deep p-type implant and the shallow n-type implant are annealed at less than 1650° C., but preferably more than about 1500°. The annealing preferably takes place for between about five minutes and about thirty minutes. It has been found that by annealing at more than about 1500° C. but less than 1650° C., the deep p-type implant laterally diffuses to the surface of the silicon carbide substrate surrounding the shallow n-type implant, without vertically diffusing the deep p-type implant to the surface of the silicon carbide substrate through the shallow n-type implant.
According to another aspect of the present invention, ramp-up time from room temperature to the anneal temperature is also controlled. Specifically, prior to annealing, the temperature of the silicon carbide substrate is increased from below about 500° C. to about 1400° C. in less than about sixty minutes but more than about twenty minutes. More specifically, the temperature of the silicon carbide substrate is increased from room temperature to the annealing temperature of less than 1650° C. in less than one hundred minutes, but more than thirty minutes. Thus, the temperature of the silicon carbide substrate is increased sufficiently rapidly to prevent annealing of defects in the silicon carbide substrate, which could prevent lateral diffusion of the deep p-type implant to the surface of the silicon carbide substrate surrounding the shallow n-type implant, without vertically diffusing the deep p-type implant to the surface of the silicon carbide substrate through the shallow n-type implant.
According to another aspect of the present invention, it has been found that the ramp-down time after annealing is also preferably controlled in order to preserve the diffused p-type implant. In particular, the temperature of the si

Affiliated with

Also associated with

Rating

Methods of fabricating silicon carbide power devices by... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods of fabricating silicon carbide power devices by..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of fabricating silicon carbide power devices by... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2579468