Methods of fabricating semiconductor structures having...

Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – On insulating substrate or layer

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S504000

Reexamination Certificate

active

06946371

ABSTRACT:
Methods for fabricating facetless semiconductor structures using commercially available chemical vapor deposition systems are disclosed herein. A key aspect of the invention includes selectively depositing an epitaxial layer of at least one semiconductor material on the semiconductor substrate while in situ doping the epitaxial layer to suppress facet formation. Suppression of faceting during selective epitaxial growth by in situ doping of the epitaxial layer at a predetermined level rather than by manipulating spacer composition and geometry alleviates the stringent requirements on the device design and increases tolerance to variability during the spacer fabrication.

REFERENCES:
patent: 4717681 (1988-01-01), Curran
patent: 4755478 (1988-07-01), Abernathey et al.
patent: 4803539 (1989-02-01), Psaras et al.
patent: 5034348 (1991-07-01), Hartswick et al.
patent: 5089872 (1992-02-01), Ozturk et al.
patent: 5198689 (1993-03-01), Fujioka
patent: 5217923 (1993-06-01), Suguro
patent: 5242847 (1993-09-01), Ozturk et al.
patent: 5334861 (1994-08-01), Pfiester et al.
patent: 5336903 (1994-08-01), Ozturk et al.
patent: 5346840 (1994-09-01), Fujioka
patent: 5442205 (1995-08-01), Brasen et al.
patent: 5496750 (1996-03-01), Moslehi
patent: 5496771 (1996-03-01), Cronin et al.
patent: 5659194 (1997-08-01), Iwamatsu et al.
patent: 5714777 (1998-02-01), Ismail et al.
patent: 5844260 (1998-12-01), Ohori
patent: 5847419 (1998-12-01), Imai et al.
patent: 5869359 (1999-02-01), Prabhakar
patent: 5877535 (1999-03-01), Matsumoto
patent: 5891769 (1999-04-01), Liaw et al.
patent: 5933741 (1999-08-01), Tseng
patent: 5998807 (1999-12-01), Lustig et al.
patent: 6008111 (1999-12-01), Fushida et al.
patent: 6066563 (2000-05-01), Nagashima
patent: 6096647 (2000-08-01), Yang et al.
patent: 6107653 (2000-08-01), Fitzgerald
patent: 6121100 (2000-09-01), Andideh et al.
patent: 6132806 (2000-10-01), Dutartre
patent: 6133124 (2000-10-01), Horstmann et al.
patent: 6159856 (2000-12-01), Nagano
patent: 6187657 (2001-02-01), Xiang et al.
patent: 6214679 (2001-04-01), Murthy et al.
patent: 6235575 (2001-05-01), Kasai et al.
patent: 6246077 (2001-06-01), Kobayashi et al.
patent: 6251780 (2001-06-01), Sohn et al.
patent: 6268257 (2001-07-01), Wieczorek et al.
patent: 6281532 (2001-08-01), Doyle et al.
patent: 6291321 (2001-09-01), Fitzgerald
patent: 6294448 (2001-09-01), Chang et al.
patent: 6306698 (2001-10-01), Wieczorek et al.
patent: 6313486 (2001-11-01), Kencke et al.
patent: 6315384 (2001-11-01), Ramaswami et al.
patent: 6316357 (2001-11-01), Lin et al.
patent: 6319805 (2001-11-01), Iwamatsu et al.
patent: 6362071 (2002-03-01), Nguyen et al.
patent: 6380008 (2002-04-01), Kwok et al.
patent: 6399970 (2002-06-01), Kubo et al.
patent: 6406986 (2002-06-01), Yu
patent: 6410371 (2002-06-01), Yu et al.
patent: 6461960 (2002-10-01), Lee
patent: 6486520 (2002-11-01), Okuno et al.
patent: 6498359 (2002-12-01), Schmidt et al.
patent: 6503833 (2003-01-01), Ajmera et al.
patent: 6509587 (2003-01-01), Sugiyama et al.
patent: 6555839 (2003-04-01), Fitzgerald
patent: 6555880 (2003-04-01), Cabral et al.
patent: 6562703 (2003-05-01), Maa et al.
patent: 6563152 (2003-05-01), Roberds et al.
patent: 6566718 (2003-05-01), Wieczorek et al.
patent: 6573126 (2003-06-01), Chen et al.
patent: 6573160 (2003-06-01), Taylor, Jr. et al.
patent: 6583015 (2003-06-01), Fitzgerald et al.
patent: 6593191 (2003-07-01), Fitzgerald
patent: 6593641 (2003-07-01), Fitzgerald
patent: 6603156 (2003-08-01), Rim
patent: 6605498 (2003-08-01), Murthy et al.
patent: 6621131 (2003-09-01), Murthy et al.
patent: 6657223 (2003-12-01), Wang et al.
patent: 6682965 (2004-01-01), Noguchi et al.
patent: 6686617 (2004-02-01), Agnello et al.
patent: 6699765 (2004-03-01), Shideler et al.
patent: 6703648 (2004-03-01), Xiang et al.
patent: 6724019 (2004-04-01), Oda et al.
patent: 6743684 (2004-06-01), Liu
patent: 2001/0001724 (2001-05-01), Kwok et al.
patent: 2001/0009303 (2001-07-01), Tang et al.
patent: 2001/0031535 (2001-10-01), Agnello et al.
patent: 2001/0045604 (2001-11-01), Oda et al.
patent: 2002/0019127 (2002-02-01), Givens
patent: 2002/0048910 (2002-04-01), Taylor, Jr. et al.
patent: 2002/0052084 (2002-05-01), Fitzgerald
patent: 2002/0056879 (2002-05-01), Wieczorek et al.
patent: 2002/0063292 (2002-05-01), Armstrong et al.
patent: 2002/0190284 (2002-12-01), Murthy et al.
patent: 2003/0113971 (2003-06-01), Nagaoka et al.
patent: 2004/0007724 (2004-01-01), Murthy et al.
patent: 2004/0014276 (2004-01-01), Murthy et al.
patent: 2004/0014304 (2004-01-01), Bhattacharyya
patent: 2004/0070035 (2004-04-01), Murthy et al.
patent: 2004/0084735 (2004-05-01), Murthy et al.
patent: 2004/0119101 (2004-06-01), Schrom et al.
patent: 2004/0142545 (2004-07-01), Ngo et al.
patent: 2004/0173815 (2004-09-01), Yeo et al.
patent: 2002-324765 (2002-11-01), None
patent: WO01/22482 (2001-03-01), None
patent: 02/13262 (2002-02-01), None
Antoniadis et al., “SOI Devices and Technology,”SOI devices and technology, Neuilly sur Seine, France, 1999, pp. 81-87.
Aoyama et al., “Facet formation mechanism of silicon selective epitaxial layer by Si ultrahigh vacuum chemical vapor deposition,”Journal of Crystal Growth, 136 (1994), pp. 349-354.
Arst et al., “Surface planarity and microstructure of low temperature silicon SEG and ELO,”Journal of Materials Research, vol. 6, No. 4 (Apr. 1991), pp. 784-791.
Cao et al., “0.18-μm Fully-Depleted Silicon-on-Insulator MOSFET's,”IEEE Electron Device Letters, vol. 18, No. 6 (Jun. 1997), pp. 251-253.
Chieh et al., “Low-Resistance Bandgap-Engineered W/Si1-xGex/Si Contacts,”IEEE Electron Device Letters, vol. 17, No. 7 (Jul. 1996), pp. 360-362.
Choi et al., “Nanoscale Ultrathin Body PMOSFETs With Raised Selective Germanium Source/Drain,”IEEE Electron Device Letters, vol. 22, No. 9 (Sep. 2001), pp. 447-448.
Choi et al., “30nm ultra-thin body SOI MOSFET with selectively deposited Ge raised S/D,”58thDevice Research Conference(2000), pp. 23-24.
Drowley et al., “Model for facet and sidewall defect formation during selective epitaxial growth of (001) silicon,”Applied Physics Letters, 52 (7) (Feb. 15, 1988), pp. 546-548.
Eaglesham et al., “Growth Morphology and the Equilibrium Shape: The Role of “Surfactants” in the Ge/Si Island Formation,”Physical Review Letters, vol. 70, No. 7 (Feb. 15, 1993), pp. 966-969.
Gallas et al., “Influence of doping on facet formation at the SiO2/Si interface,”Surface Science, 440 (1999) pp. 41-48.
Glück et al., “CoSi2and TiSi2for Si/SiGe heterodevices,”Thin Solid Films, vol. 270 (1995), pp. 549-554.
Goulding, “The selective epitaxial growth of silicon,”Materials Science and Engineering, B17 (1993), pp. 47-67.
Greve et al., “Growth Rate of Doped and Undoped Silicon by Ultra-High Vacuum Chemical Vapor Deposition,”Journal of the Electrochemical Society, vol. 138, No. 6 (Jun. 1991), pp. 1744-1748.
Huang et al., “Electrical and Compositional Properties of Co-Silicided Shallow P+-n Junction Using Si-Capped/Boron-Doped Si1-xGexLayer Deposited by UHVCME,”Journal of the Electrochemical Society, vol. 148, No. 3 (2001), pp. G126-G131.
Ilderem et al., “Very low pressure chemical vapor deposition process for selective titanium silicide films,”Appl. Phys. Lett., vol. 53, No. 8 (Aug. 22, 1988), pp. 687-689.
Ishitani et al., “Facet Formation in Selective Silicon Epitaxial Growth,”Japanese Journal of Applied Physics, vol. 24, No. 10 (Oct., 1995), pp. 1267-1269.
Jang et al., “Phosphorus doping of epitaxial Si and Si1-xGex at very low pressure,”Applied Physics Letters, 63 (12) (Sep. 20, 1993), pp. 1675-1677.
Jastrzebski, “SOI by CVD: Epitaxial Lateral Overgrowth (ELO) Process—Review,”Journal of Crystal Growth, 63 (1983), pp. 493-526.
Kamins et al., “Kinetics of selective epitaxial deposition of Si1-xGex,”Applied Physics Letters, 61 (6) (Aug. 10, 1992), pp. 669-671.
Kendel et

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Methods of fabricating semiconductor structures having... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods of fabricating semiconductor structures having..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of fabricating semiconductor structures having... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3403248

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.