Methods of fabricating semiconductor devices including dual...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

Reexamination Certificate

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C438S212000, C257SE29321

Reexamination Certificate

active

07879659

ABSTRACT:
Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.

REFERENCES:
patent: 2005/0042833 (2005-02-01), Park et al.
patent: 2005/0179030 (2005-08-01), Seo et al.
patent: 2005/0239254 (2005-10-01), Chi et al.
patent: 2006/0046407 (2006-03-01), Juengling
patent: 2006/0189043 (2006-08-01), Schulz
patent: 2006/0292787 (2006-12-01), Wang et al.
patent: 2007/0254453 (2007-11-01), Ang

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