Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2006-02-13
2008-03-25
Norton, Nadine G. (Department: 1792)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S700000, C216S088000
Reexamination Certificate
active
07348277
ABSTRACT:
There are provided methods of fabricating a semiconductor device using a sacrificial layer. The methods provide an approach to maintaining thickness distribution of the interlayer insulating layers below a sacrificial layer uniform on an overall surface of a semiconductor substrate during performing a chemical mechanical polishing (CMP) process in a damascene process. To this end, the method includes forming a pad layer, a pad interlayer insulating layer, an etch stop layer pattern, a planarized interlayer insulating layer and a sacrificial layer sequentially on a semiconductor substrate. At least one trench is formed in the sacrificial layer and the planarized interlayer insulating layer. A via contact hole is formed in the etch stop layer pattern, the pad interlayer insulating layer, and the pad layer to be disposed below the trench. A diffusion barrier layer and a conductive layer are sequentially formed to fill the trench and the via contact hole. A CMP process is performed on the conductive layer, the diffusion barrier layer, and the sacrificial layer.
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Koo Ja-Eung
Park Byung-Lyul
Dahimene Mahmoud
Mills & Onello LLP
Norton Nadine G.
Samsung Electronics Co,. Ltd.
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