Methods of fabricating profiled device isolation trenches in int

Details Methods of fabricating profiled device isolation trenches in int Methods of fabricating profiled device isolation trenches in int

1996-07-29

1999-02-02

Fourson, George R.

Fishing, trapping, and vermin destroying

437 67, 437924, H01L 2176

Patent

active

058664351

ABSTRACT:
A device isolation trench is formed in a semiconductor substrate by forming spaced apart masking regions on the substrate, leaving an exposed portion of the substrate disposed therebetween. A masking layer is formed on the masking regions and the exposed portion of the substrate. The masking layer and the substrate are then anisotropically etched for an etching time sufficient to remove the masking layer and portions of the substrate disposed between the masking regions and thereby form a device isolation trench in the substrate having rounded edges. Preferably, the step of anisotropically etching includes etching with an etchant that etches the substrate and the masking layer at approximately the same etching rate. More preferably, the substrate is silicon and the masking layer is polysilicon or amorphous silicon. The masking layer may also be high-thermal oxide (HTO) having an etching rate lower than that of the substrate. The masking regions preferably are formed from a third material having an etching rate different from that of the substrate, more preferably silicon nitride. The masking regions may be formed by forming a first layer on the substrate, forming a second layer on the substrate, and patterning the first and second layers to expose an underlying portion of the substrate and form spaced apart masking regions disposed on opposite sides of the exposed portion of the substrate. Preferably, the first layer includes silicon dioxide and the second layer includes silicon nitride.

REFERENCES:
patent: 4495025 (1985-01-01), Haskell
patent: 4577395 (1986-03-01), Shibata
patent: 4707218 (1987-11-01), Giamarco et al.
patent: 4857477 (1989-08-01), Kanamori

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