Methods of fabricating integrated circuit trench isolation regio

Details Methods of fabricating integrated circuit trench isolation regio Methods of fabricating integrated circuit trench isolation regio

1996-05-29

1999-10-26

Dang, Trung

Fishing, trapping, and vermin destroying

437 69, 437 61, 437 73, H01L 2176

Patent

active

059717688

ABSTRACT:
Narrow trenches are formed in an integrated circuit substrate. An insulation layer, preferably silicon dioxide, is formed on the substrate, a mask region, preferably silicon nitride, formed on the insulation layer, and portions of the insulation layer adjacent and underlying edge portions of the mask region removed to undermine edge portions of the mask region and leave a portion of the insulation layer underlying the mask region. A semiconductor layer, preferably polysilicon, is then formed on the substrate, extending to underlie undermined portions of the mask region, and then selectively oxidized to leave a semiconductor region underlying the mask region and form an insulation region disposed adjacent the semiconductor region. The mask region is then removed to expose the semiconductor region and the remaining portion of the insulation layer. The semiconductor region and underlying portions of the substrate are then removed to form a trench between the insulation region and the remaining portion of the insulation layer. The trench preferably is filled by forming a field insulation layer on the substrate. One portion of the field insulation layer and one portion of the remain portion of the insulation layer surrounded by an insulation-filled trench region may be removed to thereby form one active region site surrounded by a insulation-filled trench, or a plurality of portions of each layer bordered by an insulation-filled trench region may be removed to form a plurality of active region sites partially bordered by the insulation-filled trench region.

REFERENCES:
patent: 4331708 (1982-05-01), Hunter
patent: 4334348 (1982-06-01), Trenary et al.
patent: 4630343 (1986-12-01), Pierce et al.
patent: 4868136 (1989-09-01), Ravaglia
patent: 5308784 (1994-05-01), Kim et al.
patent: 5360753 (1994-11-01), Park et al.

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