Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to nonconductive state
Reexamination Certificate
2007-01-30
2008-09-02
Potter, Roy K (Department: 2822)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to nonconductive state
C438S128000
Reexamination Certificate
active
07419856
ABSTRACT:
An integrated circuit device is provided including an integrated circuit substrate having a fuse region. A window layer is provided on the integrated circuit substrate that defines a fuse region. The window layer is positioned at an upper portion of the integrated circuit device and recessed beneath a surface of the integrated circuit device. A buffer pattern is provided between the integrated circuit substrate and the window layer and a fuse pattern is provided between the buffer pattern and the window layer. Methods of forming integrated circuit devices are also described.
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“Translation of an Official Action as issued by the German Patent and Trademark Office,” corresponding to German Patent application 103 50 510.5-33, mailed May 11, 2005.
Myers Bigel & Sibley Sajovec, PA
Potter Roy K
Samsung Electronics Co,. Ltd.
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