Methods of fabricating dual fin structures

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation

Reexamination Certificate

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Details

C438S197000, C438S241000, C438S242000, C257SE21023

Reexamination Certificate

active

07902057

ABSTRACT:
Fin-FET devices and methods of fabrication are disclosed. The Fin-FET devices include dual fins that may be used to provide a trench region between a source region and a drain region. In some embodiments, the dual fins may be formed by forming a trench with fin structures on opposite sides in a protruding region of a substrate. The dual fins may be useful in forming single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.

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PCT International Search Report for Application No. PCT/US2008/071827 dated Jan. 16, 2009.
PCT International Preliminary Report on Patentability for Application No. PCT/US2008/071827 dated Feb. 11, 2010.

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