Methods of fabricating a semiconductor device having a node...

Details Methods of fabricating a semiconductor device having a node... Methods of fabricating a semiconductor device having a node...

2008-06-17

2008-06-17

Doan, Theresa T (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S586000, C257S069000, C257S368000

Reexamination Certificate

active

07387919

ABSTRACT:
In one embodiment, an intrinsic single crystalline semiconductor plug is formed to pass through a lower insulating layer using a selective epitaxial growth process employing a node impurity region as a seed layer, and a single crystalline semiconductor body pattern is formed on the lower insulating layer using the intrinsic single crystalline semiconductor plug as a seed layer. When the recessed single crystalline semiconductor plug is doped with impurities having the same conductivity type as the node impurity region, a peripheral impurity region is prevented from being counter-doped. As a result, it is possible to implement a high performance semiconductor device that requires a single crystalline thin film transistor as well as a node contact structure with ohmic contact.

REFERENCES:
patent: 5156987 (1992-10-01), Sandhu et al.
patent: 5492851 (1996-02-01), Ryou
patent: 5888872 (1999-03-01), Gardner et al.
patent: 6022766 (2000-02-01), Chen et al.
patent: 2004/0065884 (2004-04-01), Bhattacharyya
patent: 96-009163 (1996-07-01), None
patent: 2002-0096743 (2002-12-01), None
English language abstract of Korean Publication No. 96-009163.
English language abstract of Korean Publication No. 2002-0096743.

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