Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Diffusing a dopant
Reexamination Certificate
2000-08-31
2002-06-11
Le, Vu A. (Department: 2824)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Diffusing a dopant
C438S510000, C438S542000, C438S398000
Reexamination Certificate
active
06403455
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to methods of fabricating memory devices, such as a capacitor electrodes, utilizing doping anneals.
2. Description of the Related Art
Device scaling in integrated circuit design has produced an attendant decrease in the available wafer areas for devices, such as dynamic random access memory cells (“DRAMs”). As a consequence, memory cell capacitors must be squeezed into ever shrinking spaces. Because the capacitance of a memory cell capacitor is proportional to the surface area of the capacitor electrodes, the job of maintaining or even increasing device capacitance while minimum geometries continue to shrink is difficult. Because DRAM memory cell operation typically improves with increased capacitance, a variety of methods have been developed in an attempt to increase storage electrode surface areas while at the same time maintaining or reducing wafer area taken up by a memory cell. Examples of electrode designs that have greater surface area include trench and stacked capacitor configurations as well as cylindrical and finned capacitor configurations.
One method for increasing electrode surface area involves the formation of a roughened or irregular electrode surface. Methods for providing a roughened electrode surface include those employing hemispherical grain (“HSG”) silicon. In one conventional method, in-situ doped silicon is formed in amorphous or polycrystalline states on a substrate by reacting a silicon source gas such as silane (SiH
4
) or disilane (Si
2
H
6
) with a dopant gas such as phosphine (PH
3
). The doped silicon film is then masked and etched to define the desired shape of the electrode. Thereafter, an HSG silicon film is formed on the electrode to provide a greater surface area. The silicon electrode is exposed to a silicon source gas at medium temperatures to form silicon nuclei on the outer surface of the electrode. The HSG silicon film is then grown in an ultra high vacuum environment. The HSG may not grow with sufficient surface area if the dopant concentration of the capacitor electrode exceeds certain levels. Accordingly, the capacitor electrode is initially formed with a relatively light dopant level to facilitate HSG silicon growth. The additional dopant needed to provide the electrode with desirable conductivity is provided following HSG silicon growth by performing an anneal in a PH
3
ambient.
A conventional post-HSG silicon growth PH
3
anneal involves heating the wafer or substrate up to a preselected annealing temperature of about 600 to 700° C. After the wafer reaches the annealing temperature, a flow of PH
3
is introduced. The goal of the anneal is to diffuse a sufficient number of phosphorus atoms into the HSG grains to raise the dopant concentration to an acceptable level. However, manufacturing experience has demonstrated that a physical mechanism associated with the conventional phosphorus anneal is limiting phosphorus diffusion into the silicon electrode. As a result, the conventional phosphorus doping anneal following HSG silicon growth may not yield desired doping levels.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a method of fabricating a circuit device on a substrate is provided. The method includes forming a doped silicon structure on the substrate and forming a hemispherical grain silicon film on the silicon structure. The substrate is heated from a first temperature to a second temperature while undergoing exposure to a dopant gas to add a dopant to the hemispherical grain silicon film.
In accordance with another aspect of the present invention, a method of fabricating a capacitor structure on a substrate is provided. The method includes forming a doped silicon structure on the substrate and forming a hemispherical grain silicon film on the silicon structure. The substrate is heated from a first temperature to a second temperature while undergoing exposure to a dopant gas to add a dopant to the hemispherical grain silicon film. A capacitor dielectric film is formed on the hemispherical grain silicon film.
In accordance with another aspect of the present invention, a method of fabricating a circuit device on a substrate is provided. The method includes forming an access transistor; and a capacitor electrode. The capacitor electrode is fabricated by forming a doped silicon structure on the substrate, forming a hemispherical grain silicon film on the silicon structure, and heating the substrate from a first temperature to a second temperature while exposing the substrate to a dopant gas to add a dopant to the hemispherical grain silicon film.
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Balfour Scott
el-Hamdi Mohamed
Sawaya Sam E.
Semaan Louay M.
Honeycutt Timothy M.
Le Vu A.
Pyonin Adam
Samsung Austin Semiconductor, L.P.
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