Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-02-27
2007-02-27
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
10354810
ABSTRACT:
Methods of estimating routing delays between two points in a programmable logic device (PLD). The invention takes advantage of the fact that there are a finite number of possible routes (routing paths) between any two points in a PLD. In PLDs with a regular and tiled structure, such as field programmable gate arrays, the number of routes between any two points that are likely to be used by the router is relatively small. Thus, given the locations of the two points to be connected, the route most likely to be used by the router can be determined, and an associated delay can be calculated. This associated delay is then reported as the estimated routing delay. This method of delay estimation can be much more accurate than using an average delay. When the delays between possible paths vary widely, the actual delay of a connection can vary widely from the average.
REFERENCES:
patent: 5218551 (1993-06-01), Agrawal et al.
patent: 5237514 (1993-08-01), Curtin
patent: 5521837 (1996-05-01), Frankle et al.
patent: 5870309 (1999-02-01), Lawman
patent: 6263478 (2001-07-01), Hahn et al.
patent: 6272668 (2001-08-01), Teene
patent: 6385760 (2002-05-01), Pileggi et al.
patent: 6763506 (2004-07-01), Betz et al.
Cartier Lois D.
Dinh Paul
Doan Nghia M.
Maunu LeRoy D.
Xilinx , Inc.
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