Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-08-28
2010-06-08
Lin, Sun J (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07735039
ABSTRACT:
Methods of estimating delays between pins on a tile-based programmable logic device (PLD), by identifying repeat patterns and exploiting these patterns to provide accurate delay estimates. A computer-implemented method can include selecting a sample area in a tile-based PLD and constructing a delay table corresponding to the sample area. Each entry in the delay table includes a base delay value and a description of the fastest available route from a source pin in a source tile to a load pin in the sample area. To estimate a net delay, the base delay value and the description of the route are read from the delay table for specified source and load pins. One or more delay variants (e.g., pin delays and/or crossing penalties) are calculated based on the description of the route. The calculated delay variants are added to the base delay value to obtain an adjusted delay value, which is output.
REFERENCES:
patent: 6919736 (2005-07-01), Agrawal et al.
patent: 7185299 (2007-02-01), Jayaraman
Jorge Rubinstein et al.; “Signal Delay inRCTree Networks”; Copyright 1983 IEEE; IEEE Transactions on Computer-Aided-Design; Jul. 1983; pp. 202-211.
Arslan Hasan
Dasasathyan Srinivasan
Lou Meng
Rahut Anirban
Cartier Lois D.
Lin Sun J
Xilinx , Inc.
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