Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2006-08-15
2006-08-15
Mai, Son (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185270, C365S185330
Reexamination Certificate
active
07092298
ABSTRACT:
Methods of erasing a non-volatile memory device having discrete charge trap sites between a semiconductor substrate and a gate include applying a negative voltage to a gate at least partially spaced apart from a semiconductor substrate by a charge storage layer providing discrete charge trap sites. A first positive voltage is applied to a source formed in the semiconductor substrate adjacent to one sidewall of the gate. A second positive voltage, which is equal to or less than the first positive voltage, is applied to a drain formed in the semiconductor substrate adjacent to the gate and located opposite the source.
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Bae Geum-Jong
Kim Ki-Chul
Lee Nae-In
Mai Son
Mills & Onello LLP
Samsung Electronics Co,. Ltd.
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