Methods of deriving switch networks

Details Methods of deriving switch networks Methods of deriving switch networks

2011-01-25

2011-01-25

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

07877711

ABSTRACT:
A method of determining the lowest possible number of serial switches in a pull-up plane or a pull-down plane of a network implementing a logic function. The same method may be used in any multi-value function. Also, the method may be used in generating switch networks to be implemented as standard cells implementations of combinational logic cells. The minimum number of switches can also be used as a criterion for technology mapping devoted to automatic cell generation. The method is based on the use of a covering table to derive a sum of products where individual cubes have a minimum literal count.

REFERENCES:
patent: 6938223 (2005-08-01), Boppana et al.
patent: 7003738 (2006-02-01), Bhattacharya et al.
patent: 7225423 (2007-05-01), Bhattacharya et al.
V.P. Correia and A.I. Reis. “Advanced Technology Mapping for Standard-Cell Generators”. SBCC104, pp. 254-259 (2004).
R. Ebendt, W. Gunther, R. Drechsler, “Minimization of the Expected Path Length in BDDs Based on Local Changes,” Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific. 27-30 pp. 866-871. Jan. 2004.
M. Kaneko and J. Tian. “Concurrent Cell Generation and Mapping for CMOS Logic Circuits,” ASP-DAC 1997; pp. 247-252.
P. Kudva, G. Gopalakrishman, H. Jacobson and S.M. Nowick. “Synthesis of Hazard-Free Customized CMOS Complex-Gate Networks Under Multiple-Input Changes”, DAC 1996. pp. 77-82.
E.F. Moore. “Table of Four-Relay Contact Networks.” In: Logical Design of Electrical Circuits, by R.A. Higonnet and R.A. Grea. McGraw-Hill, New York, NY 1958.
S. Nagayama and T. Sasao, “On the Minimization of Longest Path Length for Decision Diagrams,” International Workshop on Logic and Synthesis (IWLS-2004), Jun. 2-4, Temecula, California, U.S.A., pp. 28-35.
Ninomiya. Catalog of four variable two-terminal switch circuits. In M.A. Harrison. Introduction to Switching and Automata Theory. App. 5. McGraw-Hill Book Company, pp. 408-472, 1965.
C. Piguet, J. Zahnd, A. Stauffer, M. Bertarionne. “A Metal-Oriented Layout Structure for CMOS Logic,” IEEE Journal of Solid-State Circuits, vol. 19, Issue 3, Jun. 1984 pp. 425-436.
R.E.B. Poli, F.R. Schneider, R.P. Ribas and A.I. Reis. “Unified theory to build cell-level transistor networks from BDDs,”. SBCCI 2003. pp. 199-204.
F.R. Schneider, R.P. Ribas, S.S. Sapatnekar, A.I. Reis, “Exact lower bound for the number of switches in series to implement a combinational logic cell,” Int'l Conf. on Computer Design Proc., pp. 357-362 (Oct. 2-5, 2005).
K. Tanaka, Y. Kambayashi, “Transduction Method for Design of Logic Cell Structure,” ASP-DAC 2004. pp. 600-603.
Olivier Coudert, et al., “New Ideas for Solving Covering Problems,” Synopsys, pp. 1-6.
Olivier Coudert, “On Solving Covering Problems,” Synopsys Inc., USA, 33rdDesign Automation Conference, 1996, pp. 1-6.
Randy H. Katz, “Contemporary Logic Design,” 1994, pp. 85-89.

Affiliated with

Also associated with

Rating

Methods of deriving switch networks does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods of deriving switch networks, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of deriving switch networks will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2723042