Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-07-02
2003-01-14
Niebling, John F. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06507932
ABSTRACT:
SUMMARY
The present invention concerns a method of simulating and/or predicting the function(s) and/or performance of a circuit, particularly an integrated circuit, and/or of increasing the accuracy of existing method(s) of simulating and/or predicting the function(s) and/or performance of a circuit. The present invention concerns a computer-readable set of instructions for performing such a method.
DISCUSSION OF THE BACKGROUND
A major failure mode of current circuit design methodologies is the simulation of different schematics than are used for a Layout Versus Schematic, or LVS, tapeout process. Currently known design techniques for predicting circuit performance from the initial circuit design require a manual process, either in the manual creation of simulation schematics from LVS schematics, or in the manual comparison of simulation and LVS schematics to determine mismatches. Disadvantages of the old technology include:
The time required to hand-create a simulation schematic
The time required to compare the layout to the simulation schematics to ensure that they have the same function
The risks inherent to a manual process
The current problem is that designers would like to model resistance and capacitance of interconnect wires for simulation purposes without being required to match these devices in the layout. However, currently available LVS tools require there to be a 1:1 mapping of schematic elements to extracted layout elements. As a result it is impossible to insert the desired parasitic elements for simulation purposes without causing LVS mismatches. With the invention of simulation tools that are capable of simulating entire integrated circuits or full chips, it is desirable to simulate using the same schematics as are used for layout.
Purpose
The present invention allows automated conversion of layout (or LVS) schematics to simulation schematics.
For instance, in the example shown in
FIG. 1
, it is desirable have one schematic which behaves like the schematic of FIG.
1
(A) for LVS, and behaves like the schematic of FIG.
1
(B) for simulation. The desired netlists for each tool (computer-readable software and/or code for modeling and/or predicting circuit function[s] and/or performance) are:
TABLE 1
Netlists for the input buffer of FIGS. 1(A)-(B).
Schematic LVS Netlist
Layout LVS Netlist
Simulation Netlist
INV1 A B
INV1 A B
INV1 A B
INV2 B C
INV2 B C
RES1 B D
INV2 D C
C1 B GND
C2 D GND
The most readily apparent problem is that the simulation and layout netlists do not match. This is true because of (a) the extra devices (i.e., the resistor and capacitors), and (b) the extra net “D” (the node D and its inherent RC characteristic[s]). It may be a relatively trivial exercise to remove the extra devices from the simulation netlist. However, it is extremely difficult to remove the extra net without causing severe LVS mismatching and/or circuit modeling problems.
This invention provides a scheme (method and computer-readable and/or processor-executable software program) to automatically convert schematics that contain a net-shorting element to a new set of schematics that contain a resistor-capacitor (RC) network in place of the net-shorting element. In the present application, a “net-shorting element” may refer to a two-terminal shorting device that is not netlisted for layout (i.e., the “imaginary” connection between node B in each of the LVS netlists in Table 1 above). Such a net-shorting element is also known colloquially as a “patch cord.” More specifically, a “net-shorting element” generally refers to a connection between two elements in the schematic having one or more inherent RC characteristic[s], which in some cases may refer to the inherent resistance and/or parasitic capacitance of the node, or of a bus section in the node.
Furthermore, in the present application, a “resistance-capacitance network” may generally refer to one or more RC circuits inserted between (a) two or more elements in the schematic, (b) two or more bus junctions in the schematic, or (c) one or more bus junctions and one or more elements in the schematic, that model one or more inherent and/or parasitic RC characteristics at the node between the schematic elements. Typically, an RC circuit in a “resistance-capacitance network” comprises a resistor and a capacitor between it and a schematic element, configured (for example) in the manner shown in FIG.
1
(B).
This technique allows a circuit designer to:
Draw only one set of schematics
Automatically create simulation schematics
Ensure that the automatically-created schematics are correct
Simulate the desired interconnect parasitics
REFERENCES:
patent: 5903469 (1999-05-01), Ho
patent: 5999726 (1999-12-01), Ho
patent: 6009252 (1999-12-01), Lipton
patent: 6099581 (2000-08-01), Sakai
patent: 6128768 (2000-10-01), Ho
patent: 6243653 (2001-06-01), Findley
Hawse Alan
Landry Greg J.
Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
Niebling John F.
Whitmore Stacey A
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