Electrical computers and digital processing systems: memory – Storage accessing and control
Reexamination Certificate
2007-04-24
2007-04-24
McLean, Kimberly N (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
C711S118000, C711S154000, C711S119000, C710S056000
Reexamination Certificate
active
10825717
ABSTRACT:
Efficient buffer cache utilization frees a data buffer as soon as data buffer processing is completed, and without losing association of the freed data buffer and a descriptor buffer. Separate free buffer link lists identify the freed data buffer and any freed descriptor buffer. The data buffer is rapidly processed then freed generally before completion of processing of the descriptor buffer, freeing the processed associated data buffer before the associated descriptor buffer is freed. The association of the processed free data buffer and the descriptor buffer may be ended to enable the more frequent use of the large capacity data buffer for other update requests.
REFERENCES:
patent: 6970921 (2005-11-01), Wang et al.
Conner Keith E.
Frey Alexander H.
Adaptec, Inc.
Martine & Penilla & Gencarella LLP
McLean Kimberly N
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