Methods forming power semiconductor devices having latch-up inhi

Details Methods forming power semiconductor devices having latch-up inhi Methods forming power semiconductor devices having latch-up inhi

1997-01-27

1999-03-09

Nguyen, Tuan H.

Semiconductor device manufacturing: process

Making regenerative-type switching device

438138, 438268, H01L 21332

Patent

active

058799672

ABSTRACT:
Methods of forming power semiconductor devices include the steps of forming a relatively highly doped latch-up inhibiting region to suppress the likelihood of parasitic thyristor latch-up in a power semiconductor device such as an insulated-gate bipolar transistor (IGBT). In particular, an insulated-gate bipolar transistor is formed by patterning an insulated gate electrode on a surface of a drift region and then implanting first dopants of second conductivity type (e.g., P-type) at a first depth into the drift region, using the gate electrode as an implant mask. The implanted first dopants are then diffused using a thermal treatment to form a base region (e.g., P- well region). Second dopants of second conductivity type are then implanted into the base region at a second depth, less than the first depth, using the insulated gate electrode as a mask. Third dopants of first conductivity type (e.g., N-type) are also implanted into the base region at a third depth, less than the second depth, using the insulated gate electrode as an implant mask. These opposite conductivity type dopants are then simultaneously diffused laterally and vertically in the base region to define a relatively wide and highly doped latch-up inhibiting region (e.g., P-type) and at least one source region disposed between the latch-up inhibiting region and the surface of the drift region. By implanting the second and third dopants using the same implant mask and then diffusing these dopants simultaneously and for the same duration, a latch-up inhibiting region can be formed as wide in the base region as the at least one source region, when the regions are viewed in transverse cross-section. This inhibits the likelihood that the P-N junction at the edge of the at least one source region will become forward biased during high forward current conduction.

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Lee et al., Latch-up Suppressed Insulate Gate Bipolar Transistor by the Deep p+ Ion Implantation under the n+ Source, Jpn. J. Appl. Phys. vol. 33, Part 1, No. 1B, Jan. 1994, pp. 563-566.

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