Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2007-08-07
2007-08-07
Pham, Thanhha S. (Department: 2813)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S734000, C438S737000, C257SE21026
Reexamination Certificate
active
10713762
ABSTRACT:
A method for forming a semiconductor device having a reduced pitch is provided. The method includes providing a substrate, forming a material layer over the substrate, forming a photoresist layer over the material layer, exposing a top surface of the photoresist layer to radiation, and forming a silylated layer over the photoresist layer. The method further includes removing a portion of the silylated layer to expose the photoresist layer, removing the photoresist layer, removing portions of the material layer using the silylated layer as a mask, and removing another portion of the silylated layer.
REFERENCES:
patent: 4751170 (1988-06-01), Mimura et al.
patent: 6001739 (1999-12-01), Konishi
patent: 6294314 (2001-09-01), Liao
patent: 6316168 (2001-11-01), Butt et al.
patent: 6350675 (2002-02-01), Chooi et al.
patent: 6429123 (2002-08-01), Tseng
patent: 6589714 (2003-07-01), Maimon et al.
patent: 2001/0049071 (2001-12-01), Merritt et al.
patent: 2003/0091936 (2003-05-01), Rottstegge et al.
patent: 2003/0224560 (2003-12-01), Odaka et al.
Macronix International Co. Ltd.
Pham Thanhha S.
Stout, Uxa Buyan & Mullins, LLP
LandOfFree
Methods for using a silylation technique to reduce cell... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods for using a silylation technique to reduce cell..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods for using a silylation technique to reduce cell... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3832999