Methods for transistor gate fabrication and for reducing...

Details Methods for transistor gate fabrication and for reducing... Methods for transistor gate fabrication and for reducing...

2002-12-31

2004-07-13

Wilczewski, M. (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S778000, C438S785000

Reexamination Certificate

active

06762114

ABSTRACT:

FIELD OF INVENTION
This invention relates generally to semiconductor devices and more particularly to methods for fabricating transistor gate structures and for reducing roughness in high-k gate dielectric layers in the manufacture of semiconductor devices.
BACKGROUND OF THE INVENTION
Field effect transistors (FETs) are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. Most common among these are metal-oxide-semiconductor field-effect transistors (MOSFETs), wherein a metal or polysilicon gate contact is energized to create an electric field in a channel region of a semiconductor body, by which current is allowed to conduct between a source region and a drain region of the semiconductor body. The source and drain regions are typically formed by adding dopants to targeted regions on either side of the channel region in a semiconductor substrate. A gate dielectric or gate oxide, such as silicon dioxide (SiO
2
), is formed over the channel region, typically by thermal oxidation. A gate electrode or gate contact (e.g., metal or doped polysilicon) is then formed over the gate dielectric, and the gate dielectric and gate contact materials are patterned to form a gate structure overlying the channel region of the substrate.
The gate dielectric is an insulator material, which prevents large currents from flowing from the gate into the channel when a voltage is applied to the gate contact, while allowing such an applied gate voltage to set up an electric field in the channel region in a controllable manner. Continuing trends in semiconductor product manufacturing include reduction in electrical device feature sizes (scaling), as well as improvements in device performance in terms of device switching speed and power consumption. MOS transistor performance may be improved by reducing the distance between the source and the drain regions under the gate electrode of the device, known as the gate or channel length, and by reducing the thickness of the layer of gate oxide that is formed over the semiconductor surface.
However, there are electrical and physical limitations on the extent to which thickness of gate dielectrics formed of SiO
2
can be reduced. For example, very thin SiO
2
gate dielectrics are prone to large gate tunneling leakage currents resulting from direct tunneling through the thin gate oxide when a gate voltage is applied. In addition, there are conventional limitations on the ability to form such thin oxide films with uniform thickness. Furthermore, thin SiO
2
gate dielectric layers provide a poor diffusion barrier to impurities, for example, and may allow high boron dopant penetration into the underlying channel region of the silicon during fabrication of the source/drain regions.
To address these shortcomings and limitations, recent efforts directed to MOS device scaling have focused on alternative dielectric materials which can be formed in a thicker layer than scaled SiO
2
, and yet which produce equivalent field effect performance. These materials generally have a dielectric constant “k” greater than that of SiO
2
, and are commonly referred to as high-k materials or high-k dielectrics. The relative performance of these high-k materials is often expressed as equivalent oxide thickness (EOT), because the alternative material layer may be thicker, while still providing the equivalent electrical effect of a much thinner layer of SiO
2
. Because the dielectric constant is higher, a thicker high-k dielectric layer can be deposited to avoid or mitigate tunneling leakage currents, while still achieving the required value of EOT that is comparable to the EOT value of a thinner layer of thermally grown SiO
2
. The reduction in transistor gate equivalent oxide thickness is sometimes referred to as EOT scaling.
High-k dielectrics are typically deposited directly over a silicon substrate to form a gate dielectric layer using chemical vapor deposition (CVD), atomic layer CVD(AL-CVD), plasma enhanced CVD (PECVD) or physical vapor deposition (PVD) processes such as sputtering. One shortcoming in forming high-k gate dielectric films using conventional CVD processes is rough surface morphology, leading to limitations of the ability to implement EOT scaling and degradation of device performance. In particular, roughness in the upper surface of the high-k dielectric layer in a transistor gate impedes EOT scaling efforts because the film appears electrically thicker in some locations and thinner in others. In this regard, thin portions of the resulting gate dielectric suffer from higher leakage currents than thicker portions, while the thicker portions have higher EOT than the thinner portions. As the high-k film thickness is scaled down, the upper surface roughness becomes more significant, whereby effective limitations arise in the ability to further scale the dielectric. Therefore, there is a need for improved gate fabrication techniques by which roughness in CVD deposited high-k dielectrics films may be reduced.
SUMMARY OF THE INVENTION
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. The invention relates to methods for fabricating transistor gate structures and high-k dielectric layers therefor using CVD deposition processes, while reducing or avoiding the undesirable effects of high-k dielectric roughness, by which improved device performance and scalability may be achieved.
In one aspect of the invention, methods are provided for fabricating transistor gate structures, in which a nucleation promotion layer is formed over a substrate or other semiconductor body. The nucleation promotion layer comprises a metal, metal silicide, or a metal silicate, which increases the density of nucleation sites on the substrate surface. During subsequent CVD deposition of high-k gate dielectric material, the high density of nucleation sites promotes uniform formation of high-k dielectric material on the substrate with reduced roughness at the top surface of the high-k layer. The nucleation promotion layer thus facilitates EOT scaling, gate leakage current reduction, and increased device reliability through improved uniformity in electrical and material properties.
The nucleation promotion layer may be formed using CVD, PVD or other deposition processes. In one possible implementation, the nucleation promotion layer and the high-k dielectric layer are both formed in-situ in a single chemical vapor deposition process chamber. The nucleation promotion layer, moreover, may be a very thin film, such as about 10 Å or less in thickness, preferably a monolayer or sub-monolayer. In addition, where the high-k dielectric layer is a compound material comprising a metal such as hafnium, the nucleation promotion layer may advantageously comprises the same metal, a silicide of the metal, or a silicate of the metal, so as to facilitate nucleation in the initial stages of high-k CVD deposition.
Another aspect of the invention provides methods for fabricating a transistor gate structure, which comprises forming an intentional interface layer over the semiconductor body, and forming a nucleation promotion layer over the intentional interface layer. Thereafter, a high-k dielectric layer is formed over the nucleation promotion layer using a chemical vapor deposition process. The nucleation promotion layer overlying the intentional interface layer provides an increased number of nucleation sites for deposition of high-k material on the intentional interface, thereby promoting uniform formation of high-k dielectric material without the degree of upper surface roughness found in conventi

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