Methods for tiling integrated circuit designs

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

11357823

ABSTRACT:
Methods for routing in the design of integrated circuits (ICs) to simplify the routing task. The method includes dividing a given IC design into a limited number of non-overlapping tiles, and then routing all tiles in parallel, each tile being independently routed by a standard router. Thereafter, routed tiles are assembled to form a routing solution for the entire IC. Details of exemplary methods are disclosed.

REFERENCES:
patent: 3617714 (1971-11-01), Kernighan
patent: 4577276 (1986-03-01), Dunlop et al.
patent: 4918614 (1990-04-01), Modarres et al.
patent: 5157618 (1992-10-01), Ravindra et al.
patent: 5224056 (1993-06-01), Chene et al.
patent: 5487018 (1996-01-01), Loos et al.
patent: 5495419 (1996-02-01), Rostoker et al.
patent: 5513124 (1996-04-01), Trimberger et al.
patent: 5519629 (1996-05-01), Snider
patent: 5587923 (1996-12-01), Wang
patent: 5822214 (1998-10-01), Rostoker et al.
patent: 5943486 (1999-08-01), Fukui et al.
patent: 6000038 (1999-12-01), Scepanovic et al.
patent: 6182272 (2001-01-01), Andreev et al.
patent: 6223328 (2001-04-01), Ito et al.
patent: 6240542 (2001-05-01), Kapur
patent: 6269469 (2001-07-01), Pavisic et al.
patent: 6289495 (2001-09-01), Raspopovic et al.
patent: 6305000 (2001-10-01), Phan et al.
patent: 6324674 (2001-11-01), Andreev et al.
patent: 6327693 (2001-12-01), Cheng et al.
patent: 6349403 (2002-02-01), Dutta et al.
patent: 6480991 (2002-11-01), Cho et al.
patent: 6519749 (2003-02-01), Chao et al.
patent: 6574782 (2003-06-01), Dewey et al.
patent: 6618846 (2003-09-01), Cheng
patent: 6865726 (2005-03-01), Igusa et al.
patent: 6889372 (2005-05-01), Teig et al.
patent: 7107561 (2006-09-01), Ali et al.
patent: 7185305 (2007-02-01), Rodman
patent: 7284223 (2007-10-01), Katagiri
patent: 7299442 (2007-11-01), Alpert et al.
patent: 2001/0018759 (2001-08-01), Andreev et al.
patent: 2002/0087940 (2002-07-01), Greidinger et al.
patent: 2003/0005398 (2003-01-01), Cho et al.
patent: 2003/0084416 (2003-05-01), Dai et al.
patent: 2003/0106036 (2003-06-01), Aoki
patent: 2003/0121017 (2003-06-01), Andreev et al.
patent: 2003/0121020 (2003-06-01), Kaptanoglu
patent: 2004/0225983 (2004-11-01), Jacques et al.
patent: 2005/0172252 (2005-08-01), Cheng et al.
patent: 2005/0193354 (2005-09-01), Ohba et al.
patent: 2005/0240893 (2005-10-01), Teig et al.
patent: 2005/0251775 (2005-11-01), Wood
patent: 2005/0273746 (2005-12-01), Malhotra et al.
patent: 2005/0273748 (2005-12-01), Hetzel et al.
patent: 2006/0036984 (2006-02-01), Mukaihira
patent: 2006/0248492 (2006-11-01), Hetzel
patent: 2007/0033562 (2007-02-01), Correale et al.
patent: 2007/0094630 (2007-04-01), Bhooshan
patent: 2007/0150846 (2007-06-01), Furnish et al.

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