Methods for storing and naming static library cells for...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07363596

ABSTRACT:
A method is provided for creating and using a library of known logic elements for facilitating the design of equivalent FPGA, structured ASIC, or other integrated circuits. Each cell in the library corresponds to a circuit element and contains equivalent circuit models of the element for implementation in different integrated circuit technologies. The cells are named and indexed using a library cell key that contains a fixed set of cell properties which uniquely characterize the function of the cell. The cell key can be used to locate cells in the library or in circuit designs, and to verify that the circuit models contained in the cell implement the correct logic function.

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“LCELL WYSIWYG Description for the Stratix II Family”, Version 1.1, Altera Corporation, Mar. 22, 2004.

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