Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2008-05-08
2009-06-02
Thai, Luan C (Department: 2891)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257SE21524, C438S014000, C438S011000, C438S018000
Reexamination Certificate
active
07541613
ABSTRACT:
A method of reducing parametric variation in an integrated circuit (IC) chip and an IC chip with reduced parametric variation. The method includes: on a first wafer having a first arrangement of chips, each IC chip divided into a second arrangement of regions, measuring a test device parameter of test devices distributed in different regions; and on a second wafer having the first arrangement of IC chips and the second arrangement of regions, adjusting a functional device parameter of identically designed field effect transistors within one or more regions of all IC chips of the second wafer based on a values of the test device parameter measured on test devices in regions of the IC chip of the first wafer by a non-uniform adjustment of physical or metallurgical polysilicon gate widths of the identically designed field effect transistors from region to region within each IC chip.
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Anderson Brent Alan
Butt Shahid Ahmad
Gabor Allen H.
Lindo Patrick Edward
Nowak Edward Joseph
International Business Machines - Corporation
Sabo William D.
Schmeiser Olsen & Watts
Thai Luan C
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