Methods for reducing semiconductor contact resistance

Details Methods for reducing semiconductor contact resistance Methods for reducing semiconductor contact resistance

1999-03-15

2001-02-06

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C438S706000, C438S720000

Reexamination Certificate

active

06184119

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to formation of contact holes and vias in the manufacture of semiconductor and more particularly to reducing contact resistance while forming the contact holes and vias.
BACKGROUND OF THE INVENTION
In the fabrication of integrated circuits, polysilicon gates are deposited on silicon substrates and source/drain junctions implanted into the silicon substrates to form the transistors. Various interlayer dielectric materials are deposited on the gates and junctions for the formation of various layers of metal interconnections. Then various etching steps are used to form holes through the interlayer dielectric materials into which conductive materials will be deposited to form the contacts and interconnections of the integrated circuits.
The etching steps need to take place in a highly selective fashion with respect to the underlying layer, i.e., the etch for a layer should remove that layer relatively quickly while not removing or very slowly removing the underlying layer. To obtain good etch selectivity, fluorocarbon plasmas containing high carbon to fluorine (C/F) ratios are usually employed.
Unfortunately, polymerization readily occurs in chemistries having high C/F ratios.
This tends to generate quantities of polymers that are not easily removed. Even the ion bombardment is insufficient to remove the polymers. The mechanism for obtaining high etch selectivity is the difference in formation of polymers on different materials.
For example, with a silicon dioxide (SiO
2
) dielectric layer and a silicon nitride (Si
3
N
4
) etch stop layer, a dual-frequency driven plasma source may be used for the contact etch process because it can achieve high etch selectivity of SiO
2
-to-Si
3
N
4
. The plasma contains a high C/F ratio which creates reactive unsaturated polymers which can stick easily to contact hole sidewall and bottom and, then, create thick polymer layers. Once the SiO
2
dielectric layer is cleared over the Si
3
N
4
stop layer, and oxygen is no longer being brought into the local environment from the SiO
2
etch process, the polymer tends to accumulate at a significant rate.
In SiO
2
etch, using C
x
F
y
as etchant, free fluorine is made responsible for the etch, forming SiF in the reaction with silicon. CF and CF
2
are precursors for the formation of the fluorocarbon polymers. This fluorocarbon layer deposition is reduced on oxide surfaces by the reaction between the oxygen released by dissociation during SiO
2
etching and the carbon in the deposited polymer. Volatile compounds such as CO, CO
2
or COF
2
are formed during the etch. On non-oxide surfaces (or Si
3
N
4
surface) polymer layers should be formed, protecting the surface from free fluorine.
However, a potential drawback of leaving a thick polymer layer over Si
3
N
4
is to lower the etch selectivity of Si
3
N
4
-to-silicide (TiSi
x
). The silicide is formed on the polysilicon gate to provide low contact resistance bonding to the conductive contact metals. Fluorine from the deposited polymer can reduce, substantially, the etch selectivity of Si
3
N
4
-to-TiSi
x
on fully processed wafers. This can cause open or high contact resistances.
A method for increasing the etch selectivity and the process window for etching semiconductor contacts has been long sought, but has long eluded those skilled in the art.
DISCLOSURE OF THE INVENTION
The polymerization effects in fluorocarbon plasmas during high selectively sub-quarter-micron contact hole etching create thick polymer layers. It has been discovered that these thick polymer layers, formed during the dielectric removal step, reduce the etch selectivity to various underlayer dielectric layers, and which could increase contact resistance. The present invention provides for removal of the polymer after dielectric etch prior to the etch step for the next underlying layer to improve the etch selectivity and reduce the contact resistance.
The polymerization effects in high C/F ratio fluorocarbon plasmas during high selectively sub-quarter-micron contact hole etching of silicon dioxide layer create thick polymer layers. It has been discovered that these thick polymer layers reduce the etch selectivity of the etching of silicon dioxide to nitride layers, and possibly nitride to silicide layers as well, and it results in contact resistance increase. The present invention provides for removal of the polymer after silicon dioxide etch prior to the etch step for the next underlying layer to improve the etch selectivity and reduce the contact resistance.
The polymerization effects in high C/F ratio fluorocarbon plasmas during high selectively sub-quarter-micron contact hole etching of silicon dioxide (SiO
2
) create thick polymer layers. It has been discovered that fluorine from the polymer will severely degrade the etch selectivity of SiO
2
-to-Si
3
N
4
, and possibly Si
3
N
4
-to-TiSi
x
, and increase contact resistance. The present invention provides for removal of the polymer after SiO
2
etch prior to the etch step for the next underlying layer to improve the etch selectivity and reduce the contact resistance.
This polymerization effect is even more important when the technology goes to sub-quarter-micron because of the thinner underlying layers of silicon dioxide layers, such as nitride etch stop and silicide layers. Therefore, the elimination of the polymerization effects after silicon dioxide etch prior to the etch step for the next underlying layer becomes even useful in the structuring of a robust process in the future.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1
(PRIOR ART) is a partial close-up section of a semiconductor device gate with a contact hole subject to polymer buildup where the device is in the center of a semiconductor wafer;
FIG. 2
(PRIOR ART) is a partial close-up section of a semiconductor device gate with a contact hole subject to polymer buildup where the device is near the edge of the semiconductor wafer;
FIG. 3
(PRIOR ART) is a partial close-up section of a semiconductor device diffusion contact with a contact hole subject to polymer buildup where the device is in the center of the semiconductor wafer;
FIG. 4
(PRIOR ART a partial close-up section of a semiconductor device diffusion contact with a contact hole subject to polymer buildup where the device is near the edge of the semiconductor wafer.
FIG. 5
is a partial close-up section of a semiconductor device gate with a contact hole subject to polymer buildup and elimination of fluorine where the device is in the center of the semiconductor wafer;
FIG. 6
is a partial close-up section of a semiconductor device gate with a contact hole subject to polymer buildup and elimination of fluorine where the device is near the edge of the semiconductor wafer;
FIG. 7
is a partial close-up section of a semiconductor device diffusion contact with a contact hole subject to polymer buildup and elimination of fluorine where the device is in the center of the semiconductor wafer;
FIG. 8
is a partial close-up section of a semiconductor device diffusion contact with a contact hole subject to polymer buildup and elimination of fluorine where the device is near the edge of the semiconductor wafer;
FIG. 9
is a partial close-up section of a semiconductor device gate with a contact hole subject to polymer buildup according to the present invention and elimination of fluorine where the device is in the center of the semiconductor wafer;
FIG. 10
is a partial close-up section of a semiconductor device gate with a contact hole subject to polymer buildup removal according to the present invention and elimination of fluorine where the device is near the edge of the semiconductor wafer;
FIG. 11
is a partial close-up section of a semiconductor device diffusion contact with a contact hole subject to polymer buildup removal according to the present in

Affiliated with

Also associated with

Rating

Methods for reducing semiconductor contact resistance does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods for reducing semiconductor contact resistance, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods for reducing semiconductor contact resistance will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2596277