Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1996-12-18
2001-10-30
Woodward, Michael P. (Department: 1631)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S706000, C438S710000, C438S712000, C438S720000, C438S732000
Reexamination Certificate
active
06309979
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to the etching of a conductive layer on a substrate. More particularly, the invention relates to methods for protecting a semiconductor substrate from charging damage while etching a conductive layer.
In semiconductor IC fabrication, devices such as component transistors are formed on a wafer or a substrate, which is typically made of silicon. Successive layers of various materials are deposited on the substrate to form a layer stack. These layers are deposited and etched to form the desired components. Metallic interconnection lines, which are etched from the conductive layer of the layer stack, are then employed to couple components together to form the desired circuit.
In etching the various layers of the layer stack, there is employed in the prior art high density plasma etching processes. Advantages associated with high density plasma etching, which are well known, include improved etch rates and etch directionality. It has been found, however, that the etching of the conductive layer may lead to unintended negative consequences.
For example, it has been discovered that the etching of a conductive layer can result in a plasma charging problem Plasma charging is caused when the certain layer, e.g., the conductive layer, picks up positive charges while etching, thereby causing electrons from within the substrate to flow toward the positively charged layer. As is knows, the flow of electrons induces current flow in the opposite direction. The plasma-induced current may flow through some other layers underlying the conductive layer, thereby potentially causing plasma charging damage.
The above plasma charging problem may be better understood with reference to FIG.
1
. In
FIG. 1
, there is shown a plasma region
100
, representing the region of the high density plasma processing chamber in which a plasma is struck with reactive etchant source gases. Within plasma region
100
, there are reactive ions comprising positive ions
102
and electrons
104
. During etching, the reactive ions come into contact with the layers disposed on a substrate
106
and, depending on the selectivities of the layers contacted, may react with some of the contacted layers. In the example of
FIG. 1
, the layers are shown as photoresist layer
108
, conductive layer
110
, and field oxide layer
112
. In open area
114
, some of the reactive ions may even come in contact with the surface of substrate
106
.
Positive ions
102
typically follow the potential field that is set up within the high density plasma processing chamber and impact substrate
106
, as well as the layers that are disposed thereon, in a generally vertical direction. Consequently, positive ions are said to be anisotropic and are able to penetrate the narrow trenches
122
and
124
between adjacent columns of photoresists, e.g., columns
116
,
118
and
120
in photoresist layer
108
to impart a generally positive polarity to underlying conductive layer
110
.
Electrons
104
, on the other hand, tend to be more isotropic, i.e., they do not follow the potential field set up within the high density plasma processing chamber. Accordingly, a greater percentage of electrons
104
tends to impact the sidewalls of the photoresist columns
116
,
118
and
120
, thereby imparting a generally negative charge to photoresist layer
108
.
The etch rate during the high density plasma process is different for the open area
114
than it is for a narrow trench area, e.g., area
122
located between columns
116
and
118
and a narrow trench area
124
between columns
118
and
120
. Because of its faster etch rate the conductive layer will be removed from the open area
114
before it is removed from the narrow trench areas
122
and
124
. Once the conductive layer is removed the semiconductor substrate
106
can be directly exposed to the plasma.
Since conductive layer
110
is positively charged, electrons from substrate
106
tend to be attracted thereto. The flow of electrons toward the positively charged conductive layer, e.g., toward a region
126
, induces current
128
flow in the opposite direction, e.g., from conductive layer
110
to substrate
106
through region
126
. The current
128
path is completed as electrons from plasma region
100
flow into substrate
106
through open area
114
. If the current
128
is sufficiently high, components in its path may be destroyed or undesirably altered in its electrical properties.
By way of example, region
126
may, in the case of a MOS (metal oxide semiconductor) transistor, represent a gate oxide region. This gate oxide region
126
may be relatively thin, e.g., about 150 angstroms or below, and may be easily damaged or even destroyed in the presence of even a small plasma-induced current. Alternatively or additionally, the plasma-induced current through gate oxide region
126
may cause charges to be trapped underneath gate oxide region
126
. The presence of the trapped charge may undesirably alter the amount of current required to turn on the fabricated transistor. In some cases, the alteration may even render the fabricated transistor unusable.
In view of the foregoing, there are desired improved methods and apparatus therefor that facilitate the etching of the conductive layer in a high density plasma processing chamber. The improved methods and apparatus therefor preferably etches through selected portions of the conductive layer while minimizing charging damage from plasma-induced current.
SUMMARY OF THE INVENTION
The present invention relates to, in one embodiment, a method in a high density plasma chamber for protecting a semiconductor substrate from charging damage from plasma-induced current through the substrate while etching through a selected portion of a conductive layer above the substrate. The method includes performing a bulk etch at least partially through the selected portion of the conductive layer using a first power setting for a plasma generating source of the high density plasma chamber. The method further includes performing a clearing etch through the selected portion of the conductive layer using a second power setting for the plasma generating source. In accordance with this embodiment, the second power setting is substantially minimized to reduce the charging damage.
In another embodiment, the invention relates to a method for protecting a semiconductor substrate from charging damage from plasma-induced current through the substrate while etching through a selected portion of a conductive layer above the substrate. The method includes performing, in a first plasma chamber, a bulk etch at least partially through the selected portion of the conductive layer using a first power setting for a first plasma generating source of the first plasma chamber. There is further included performing, in a second plasma chamber, a clearing etch through the selected portion of the conductive layer using a second power setting for a second plasma generating source of the second plasma chamber. The second power setting is preferably substantially lower than the first power setting to reduce the charging damage.
In yet another embodiment, the invention relates to a method, in a high density plasma chamber that includes a primary plasma generating source for dispensing etchant chemicals, for protecting a semiconductor substrate from charging damage from plasma-induced current through the substrate while etching through a selected portion of a conductive layer above the substrate. The method includes performing a bulk etch at least partially through the selected portion of the conductive layer with a first gap distance between the primary plasma generating source and the substrate. The method further includes performing a clearing etch through the selected portion of the conductive layer with a second gap distance between the primary plasma generating source and the substrate greater than the first gap distance. In this manner, the selected portion of the conductive layer is etched through with lower density plasma durin
Atzei Luisarita
Patrick Roger
Siu Stanley C.
Beyer Weaver & Thomas LLP
Lam Research Corporation
Woodward Michael P.
Zeman Mary K.
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