Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-08-18
2010-02-02
Kim, Hong (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S133000, C711S138000, C711S144000, C713S320000
Reexamination Certificate
active
07657708
ABSTRACT:
Methods for reducing data cache access power in a processor. In an embodiment, a micro tag array is used to store base address or base register data bits, offset data bits, a carry bit, and way selection data bits associated with cache accesses. When a LOAD or a STORE instruction is fetched, at least a portion of the base address and at least a portion of the offset of the instruction are compared to data stored in the micro tag array. If a micro tag array hit occurs, the micro tag array generates a cache dataram enable signal. This signal activates only the cache dataram that stores the needed data.
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Kandem
Kinter Ryan C.
Knoth Matthias
Kim Hong
MIPS Technologies Inc.
Sterne Kessler Goldstein & Fox PLLC
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