Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2011-01-18
2011-01-18
Doan, Nghia M (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C005S018100
Reexamination Certificate
active
07873926
ABSTRACT:
Methods for analyzing timing of an integrated circuit using block-based static statistical timing analysis and for practical worst test definition and debug. The method includes building a timing graph, determining a slack for each of the nodes in the timing graph, and identifying a statistically worst slack for at least one of the nodes. The method further includes replacing this statistically worst slack with a proxy worst slack.
REFERENCES:
patent: 5095454 (1992-03-01), Huang
patent: 5636372 (1997-06-01), Hathaway et al.
patent: 6321362 (2001-11-01), Conn et al.
patent: 7086023 (2006-08-01), Visweswariah
patent: 7111260 (2006-09-01), Visweswariah
patent: 7428716 (2008-09-01), Visweswariah
patent: 2005/0065765 (2005-03-01), Visweswariah
patent: 2005/0066296 (2005-03-01), Visweswariah
patent: 2005/0066298 (2005-03-01), Visweswariah
patent: 2006/0085775 (2006-04-01), Chang et al.
patent: 2006/0101361 (2006-05-01), Foreman et al.
patent: 2007/0226667 (2007-09-01), Chadwick, Jr. et al.
patent: 2007/0234256 (2007-10-01), Chang et al.
Chopra, et al., “A New Statistical Max Operation for Propagating Skewness in Statistical Timing Analysis”, Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided Design Table of Contents, San Jose, CA, Session: Statistical Timing Analysis Table of Contents, pp. 237-243.
Jess, et al., “Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits”, Design Automation Conference, Jun. 2003, Anaheim, CA, pp. 932-937.
Visweswariah, et al., “First-Order Incremental Block-Based Statistical Timing Analysis”, Proceedings of the 41st Design Automation Conference, Jun. 2004, San Diego, CA, pp. 331-336.
Buck Nathan C.
Foreman Eric A.
Gregerson James C.
Hemmett Jeffrey G.
Doan Nghia M
International Business Machines - Corporation
Wood Herron & Evans LLP
LandOfFree
Methods for practical worst test definition and debug during... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods for practical worst test definition and debug during..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods for practical worst test definition and debug during... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2711807