Methods for post offset spacer clean for improved selective...

Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S341000, C257SE21090, C257SE21020

Reexamination Certificate

active

10969769

ABSTRACT:
A gate structure is formed overlying a substrate. A source/drain region of the substrate is exposed to a soluction comprising ammonium hydroxide, hydrogen peroxide, and deionized water to etch an upper-most semiconductor porton of the source/drain region.

REFERENCES:
patent: 4933295 (1990-06-01), Feist
patent: 5298454 (1994-03-01), D'Asaro et al.
patent: 5319232 (1994-06-01), Pfiester
patent: 5387309 (1995-02-01), Bobel et al.
patent: 5556462 (1996-09-01), Celii et al.
patent: 5670018 (1997-09-01), Eckstein et al.
patent: 5696012 (1997-12-01), Son
patent: 5710450 (1998-01-01), Chau et al.
patent: 5773328 (1998-06-01), Blanchard
patent: 5854136 (1998-12-01), Huang et al.
patent: 5902125 (1999-05-01), Wu
patent: 5956590 (1999-09-01), Hsieh et al.
patent: 6024794 (2000-02-01), Tamamura et al.
patent: 6074939 (2000-06-01), Watanabe
patent: 6133093 (2000-10-01), Prinz et al.
patent: 6159422 (2000-12-01), Graves et al.
patent: 6165826 (2000-12-01), Chau et al.
patent: 6165857 (2000-12-01), Yeh et al.
patent: 6228730 (2001-05-01), Chen et al.
patent: 6251764 (2001-06-01), Pradeep et al.
patent: 6277700 (2001-08-01), Yu et al.
patent: 6313017 (2001-11-01), Varhue
patent: 6346447 (2002-02-01), Rodder
patent: 6346468 (2002-02-01), Pradeep et al.
patent: 6380043 (2002-04-01), Yu
patent: 6403434 (2002-06-01), Yu
patent: 6436841 (2002-08-01), Tsai et al.
patent: 6440851 (2002-08-01), Agnello et al.
patent: 6444578 (2002-09-01), Cabral et al.
patent: 6451693 (2002-09-01), Woo et al.
patent: 6479358 (2002-11-01), Yu
patent: 6679946 (2004-01-01), Jackson et al.
patent: 6726767 (2004-04-01), Marrs et al.
patent: 6777759 (2004-08-01), Chau et al.
patent: 6890391 (2005-05-01), Aoki et al.
patent: 6924518 (2005-08-01), Iinuma et al.
patent: 6946371 (2005-09-01), Langdo et al.
patent: 6979622 (2005-12-01), Thean et al.
patent: 7014788 (2006-03-01), Fujimura et al.
patent: 2001/0012693 (2001-08-01), Talwar et al.
patent: 2002/0135017 (2002-09-01), Vogt et al.
patent: 2002/0137297 (2002-09-01), Kunikiyo
patent: 2002/0142616 (2002-10-01), Giewont et al.
patent: 2002/0171107 (2002-11-01), Cheng et al.
patent: 2003/0042515 (2003-03-01), Xiang et al.
patent: 2003/0098479 (2003-05-01), Murthy et al.
patent: 2004/0041216 (2004-03-01), Mori et al.
patent: 2004/0119102 (2004-06-01), Chan et al.
patent: 2005/0121719 (2005-06-01), Mori
patent: 2005/0252443 (2005-11-01), Tsai et al.
patent: 06326049 (1994-11-01), None
Nojiri, et al. “Bias-Dependent Etching of Silicon In Aqueous Ammonia,” Central Engineering Lab. Nissan Motor Co., 1991IEEE, pp. 136-139, Yokosuka, Japan.
Branebjerg, et al. “Dopant Selective HF Anodic Etching of Silicon,” Mesa-Institute, University of Twente, 1991 IEEE, pp. 221-226, Enschede, The Netherlands.
Wang, et al., “Selective Etching of N-Type silicon Using Pulsed Potential Anodization,” General Motors Research Lab., 1991 IEEE, pp. 819-822, Warren, Michigan.
van den Meerakker, et al., “A Mechanistic tudy of Silicon Etchingin NH3/H2O2 Cleaning Solutions,” Philips Research Lab., J. Electrochem. Soc., vol. 137, No. 4, pp. 1239-1243 Eindhoven The Netherlands.
Besser, et al., “Silicides For The 65 nm Technology Node,” MRS symposum Proc. 766 (2003), Technology Development Group, Advanced Micro Devices, Inc. Austin, TX.
Van Meer et al., “70 nm Fully-Depleted SOI CMOS Using A New Fabrication Scheme: The Spacer/Replacer Scheme,” IMEC, Leuven, Belgium, (Jun. 2002).
Wolf et al., “Silicon Processing for the VLSI Era vol. 1: Process Technology”, ISBN 0-961672-3-7, University of California, Sunset Beach, California, pp. 521-542, (1986).
Chau et al., “A 50nm Depleted-Substrate CMOS Transistor (DST),” 2001 IEEE, Intel Corporation, Hillsboro, Oregon, (2001).
Cohen et al., “A Self-Aligned Silicide Process Utilizing ION Implants for Reduced Silicon Consumption And Control of the Silicide Formation Temperature,” vol. 716, 2002 Materials Research Society, pp. B1.7.1-B1.7.6, Yorktown Heights, New York, (2002).
Ghani et al., “A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors,” 2003 IEEE, 3 pages, (2003).
van den Meerakker, et al., “A Mechanistic tudy of Silicon Etchingin NH3/H202 Cleaning Solutions,” Philips Research Lab., J. Electrochem. Soc., vol. 137, No. 4, pp. 1239-1243 Eindhoven The Netherlands, Apr. 1990).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Methods for post offset spacer clean for improved selective... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods for post offset spacer clean for improved selective..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods for post offset spacer clean for improved selective... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3738825

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.