Methods for placement which maintain optimized behavior,...

Details Methods for placement which maintain optimized behavior,... Methods for placement which maintain optimized behavior,...

2008-05-20

2008-05-20

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

11180740

ABSTRACT:
A method for determining placement of circuitry during integrated circuit design is presented. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list. A composite net weight is determined for said timing paths, the composite net weight being in response to the plurality of individual net weights. Concurrently therewith it is advantageous to utilize our new method of improvements of concurrently proceeding to improve wireability of said design by additional timing optimization and net weight mapping modification steps.

REFERENCES:
patent: 5218551 (1993-06-01), Agrawal et al.
patent: 5237514 (1993-08-01), Curtin
patent: 5251147 (1993-10-01), Finnerty
patent: 5521837 (1996-05-01), Frankle et al.
patent: 5666290 (1997-09-01), Li et al.
patent: RE35671 (1997-11-01), Hartoog
patent: 6086631 (2000-07-01), Chaudhary et al.
patent: 6480991 (2002-11-01), Cho et al.
patent: 6493854 (2002-12-01), Chowdhury et al.
patent: 6601226 (2003-07-01), Hill et al.
patent: 6757877 (2004-06-01), Stenberg et al.
patent: 6836753 (2004-12-01), Silve
patent: 7120888 (2006-10-01), Curtin et al.
patent: 7207020 (2007-04-01), Fung et al.
patent: 7257795 (2007-08-01), Fung et al.
patent: 7308664 (2007-12-01), Fung et al.
patent: 2001/0010090 (2001-07-01), Boyle et al.
patent: 2003/0005398 (2003-01-01), Cho et al.
patent: 2006/0010411 (2006-01-01), Curtin et al.
patent: 2006/0010413 (2006-01-01), Curtin et al.
patent: 2006/0010415 (2006-01-01), Curtin et al.
patent: 2006/0015836 (2006-01-01), Curtin et al.
patent: 2006/0095879 (2006-05-01), Brahme et al.
patent: 2006/0277515 (2006-12-01), Curtin et al.
Ren et al., “Sensitivity Guided Net Weighting for Placement-Driven Synthesis”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, No. 5, May 2005, pp. 711-721.

Affiliated with

Also associated with

Rating

Methods for placement which maintain optimized behavior,... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods for placement which maintain optimized behavior,..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods for placement which maintain optimized behavior,... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3930607