Methods for normalizing strain in a semiconductor device

Details Methods for normalizing strain in a semiconductor device Methods for normalizing strain in a semiconductor device

2008-03-27

2010-10-19

Arora, Ajay K (Department: 2892)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S187000, C257SE21640, C257SE21633

Reexamination Certificate

active

07816274

ABSTRACT:
The electrical performance enhancing effects of inducing strain in semiconductor devices is made substantially uniform across a substrate having a varying population density of device components by selectively spacing apart the strain-inducing structures from the effected regions of the semiconductor devices depending upon the population density of device components. Differing separation distances are obtained by selectively forming sidewall spacers on device components, such as MOS transistor gate electrodes, in which the sidewall spacers have a relatively small width in regions having a relatively high density of device components, and a relatively larger width in regions having a relatively low density of device components. By varying the separation distance of strain-inducing structures from the effected components, uniform electrical performance is obtained in the various components of the devices in an integrated circuit regardless of the component population density.

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Yuan, et al., “A 45nm low cost low power platform by using integrated dual-stress-liner technology”, Symposium on VLSI Technology Digest of Technical Papers, 2006.

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