Methods for multi-modal wafer testing using edge-extended...

Details Methods for multi-modal wafer testing using edge-extended... Methods for multi-modal wafer testing using edge-extended...

2007-06-05

2008-11-25

Patel, Paresh (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S765010

Reexamination Certificate

active

07456643

ABSTRACT:
Access to integrated circuits of a wafer for concurrently performing two or more types of testing, is provided by bringing a wafer and an edge-extended wafer translator into an attached state. The edge-extended wafer translator having wafer-side contact terminals and inquiry-side contact terminals disposed thereon, a first set of wafer-side contact terminals being electrically coupled to a first set of inquiry-side contact terminals, and a second set of wafer-side contact terminals being electrically coupled to a second set of inquiry-side contact terminals. The edge-extended wafer translator having a central portion generally coextensive with the attached wafer, and an edge-extended portion extending beyond the boundary generally defined by the outer circumferential edge of the wafer. A first set of pads of at least one integrated circuit is electrically coupled to the first set of wafer-side contact terminals, and a second set of pads of the integrated circuit is electrically coupled to the second set of wafer-side contact terminals. The edge-extended wafer translator may be shaped such that its edge-extended portion is not coplanar with the central portion thereof.

REFERENCES:
patent: 4975638 (1990-12-01), Evans et al.
patent: 6097199 (2000-08-01), Jeng et al.
patent: 6911835 (2005-06-01), Chraft et al.
patent: 7098680 (2006-08-01), Fukushima et al.

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