Methods for measurement and prediction of hold-time and...

Details Methods for measurement and prediction of hold-time and... Methods for measurement and prediction of hold-time and...

2008-09-09

2008-09-09

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

11377778

ABSTRACT:
Techniques for estimating a risk of incorrect timing analysis results for signal paths having cells with inputs tied together are described. Signal paths having cells with tied input pins are identified in a circuit. A timing analysis on the signal paths is run to identify the worst case delay through the signal paths. The risk to the signal paths of incorrect timing analysis results due to the cells with tied input pins is estimated by a tied input pin analysis tool. Metrics that quantify timing failure risk associated with signal paths is provided in the form of a set of equations. These equations are embedded into a process allowing automated multi-modal, multi power voltage temperature analysis for the identification of high risk paths.

REFERENCES:
patent: 5883808 (1999-03-01), Kawarabayashi
patent: 7191417 (2007-03-01), Luo et al.
patent: 7243323 (2007-07-01), Williams et al.
patent: 7278126 (2007-10-01), Sun et al.

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