Methods for manufacturing stacked gates including...

Details Methods for manufacturing stacked gates including... Methods for manufacturing stacked gates including...

2003-02-06

2004-03-16

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S694000

Reexamination Certificate

active

06706613

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to semiconductor device manufacturing methods, and more particularly to methods of manufacturing semiconductor devices including stacked genes having oxide
itride/oxide (ONO) interlayer dielectrics.
BACKGROUND OF THE INVENTION
Stacked gate structures including ONO interlayer dielectrics are widely used, for example, in flash memory devices, such as Electrically Erasable and Programmable Read-Only Memory (EEPROM) devices. In particular, a memory cell of an EEPROM device may include a stacked gate structure including a floating gate adjacent a silicon substrate, an ONO interlayer dielectric on the floating gate opposite the silicon substrate and a control gate on the ONO interlayer dielectric opposite the floating gate. In these flash memories, data storage may be accomplished by storing electrons in the floating gate or extracting electrons from the floating gate, while appropriate voltages are applied to the control gate and/or the substrate. The design and operation of flash memory devices such as EEPROMs are well known to those having skill in the art and need not be desired further herein.
FIG. 1
is a cross-sectional view showing a non-volatile semiconductor memory device that is fabricated according to a conventional manufacturing method.
Referring to
FIG. 1
, a tunnel oxide film
12
(such as a gate oxide film) is formed in a semiconductor substrate
10
, such as a silicon semiconductor substrate, that is divided into an active region and a field region. After a first polysilicon film is coated on the tunnel oxide film, the first polysilicon film is partially removed from the field region through a photolithography process, so that the floating gates formed in adjacent active regions are electrically insulated from each other.
Then, an oxide
itride/oxide (ONO) layer
16
is formed on the substrate
10
having the resultant structure. The ONO layer
16
serves as an interlayer dielectric, and includes a first oxide film, a nitride film, and a second oxide film.
A second polysilicon film and a metal silicide film are successively formed on the ONO layer
16
. After a hard mask layer for patterning the gate is formed on the metal silicide film, the hard mask layer is patterned to form a hard mask pattern
22
.
The metal silicide film, the second polysilicon film, the ONO layer
16
, and the first polysilicon film are successively etched using the hard mask pattern
22
as an etching mask. Thus, a stacked gate of a memory cell including a floating gate
14
and a control gate
25
with the ONO layer
16
therebetween, is formed on the substrate
10
. The floating gate
14
includes a first polysilicon pattern, and the control gate
25
includes a second polysilicon pattern
18
and a metal silicide pattern
20
.
After the patterning process for forming the stacked gate is completed, a process for oxidizing the gate sidewalls is executed in order to cure the damage to the lateral (end) portions of the ONO layer
16
and the damage to the substrate
10
under the edge portion of the floating gated
14
that may be caused by the prior etching process. The process for oxidizing the gate is conventionally performed at a temperature of more than approximately 600° C. about 3 hours. As a result, an oxide film
26
is formed on the surface of the substrate
10
, on the sidewalls of the floating gate
14
, and on the sidewalls of the control gate
25
, by an oxidation process. The oxide film
26
also can function as a buffer layer for reducing or preventing the substrate
10
from being damaged during a successive ion implantation process for forming a source/drain region.
In general, the oxide film is formed in accordance with the following reaction equation:
Si+O
2
, H
2
O→SiO
2
.
As shown the above reaction equation, oxidizing agents are diffused into a layer including silicon to produce an oxidation reaction between the silicon and the oxidizing agents. Thus, the oxidation reaction occurs at the sidewalls of the floating gate
14
, at the interface between the floating gate
14
and the ONO layer
16
, at the interface between the control gate
15
and the ONO layer
16
, and at the sidewalls of the control gate
25
.
However, the oxidizing agents may permeate from the upper portion of the control gate
25
to the central portion B of the ONO layer
16
so that a bird's beak A may occur as shown in
FIG. 1
, since the oxidation process is performed at a temperature of more than 600° C. for a long time. In the same manner, the oxidizing agents may permeate from the upper portion of the floating gate
14
to the central portion B of the ONO layer
16
so that a bird's beak A further occurs. As the thickness of the ONO layer
16
increases due to the bird's beak, the capacitance between the floating and the control gates
14
and
25
, respectively, may be reduced. In addition, the programming speed and/or the cell current may be reduced. Furthermore, because the electric field may be concentrated at the portion where the ONO layer
16
is thin, dielectric breakdown of the ONO layer
16
may occur.
SUMMARY OF THE INVENTION
Some embodiments of the present invention provide methods for manufacturing a semiconductor device including a stacked gate having stacked gate sidewalls and an oxide
itride/oxide (ONO) interlayer dielectric. According to some embodiments of the invention, pre-annealing is performed on the stacked gate in a first atmosphere comprising nitrogen. At least a portion of the stacked gate sidewalls of the stacked gate that has been pre-annealed is oxidized. Post-annealing is then performed on the stacked gate including the stacked gate sidewalls that have been oxidized, in a second atmosphere comprising nitrogen.
In other embodiments of the invention, a temperature of a batch furnace having therein a semiconductor device that includes a stacked gate having stacked gate sidewalls and an ONO interlayer dielectric, is raised in an inert gas atmosphere. Pre-annealing is performed on the stacked gate in the batch furnace in a first atmosphere that comprises nitrogen. At least a portion of the stacked gate sidewalls of the stacked gate that has been pre-annealed is oxidized. Post-annealing is performed on the stacked gate including the stacked gate sidewalls that have been oxidized, in a second atmosphere comprising nitrogen.
According to still other embodiments of the invention, a temperature of a single wafer rapid oxidation apparatus having therein a semiconductor device that includes a stacked gate having stacked gate sidewalls and an ONO interlayer dielectric, is raised in an inert gas atmosphere. At least a portion of the stacked gate sidewalls of the stacked gate is oxidized in the single wafer rapid oxidation apparatus in which the temperature has been raised. Post-annealing then is performed on the stacked gate including the stacked gate sidewalls that have been oxidized, in an atmosphere comprising nitrogen.
In all of the above embodiments, the first and second atmospheres may comprise at least one of N
2
, N
2
O and NO. Moreover, in all of the above embodiments, the first and second atmospheres may comprise different gasses. Also, in all of the above embodiments, the pre-annealing, oxidizing and post-annealing may be performed at the same temperature. Finally, in all of the above embodiments, the inert gas atmosphere may comprise at least one of N
2
, N
2
O, NO, Ar and He.
In some embodiments, the pre-annealing, oxidizing and post-annealing are performed in a single processing chamber. In other embodiments, the pre-annealing and the oxidizing are performed in separate processing chambers. In still other embodiments, the raising, the pre-annealing, the oxidizing and the post-annealing are all performed in a batch furnace. In yet other embodiments, the oxidizing and the post-annealing are performed in a single wafer rapid oxidation apparatus. Finally, in still other embodiments, the post-annealing is performed in a batch furnace.


REFERENCES:
patent: 6133150 (2000-10-01), Nakajima et al.
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