Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2002-06-26
2004-01-13
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S239000, C438S255000, C438S386000, C438S393000, C438S396000, C438S665000
Reexamination Certificate
active
06677217
ABSTRACT:
RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 2001-36584, filed Jun. 26, 2001, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.
FIELD OF THE INVENTION
The present invention relates to integrated circuit capacitors and methods for manufacturing the same, and more particular to Metal-Insulator-Metal (MIM) capacitors and methods for manufacturing the same
BACKGROUND OF THE INVENTION
MIM capacitors are widely used in integrated circuit devices. As is well known to those having skill in the art, a MIM capacitor comprises spaced apart first (lower) and second (upper) metal layers (electrodes) and a dielectric layer therebetween. As the integration density of integrated circuit devices continues to increase, the area occupied by an individual device may continue to decrease. Thus, in MIM capacitors, it may be desirable to increase the capacitance by increasing the effective area of the capacitor, by forming a thin dielectric layer and/or by forming the dielectric layer of a material having high dielectric constant. Unfortunately, a thin film dielectric may produce decreased reliability and high dielectric constant dielectrics may require new manufacturing processes.
In order to increase the effective area of a capacitor, the capacitor may be formed to have a three-dimensional structure, such as a fin structure, a cylinder structure and/or a trench structure. In particular, in the case of a metal-insulator-semiconductor (MIS) capacitor, hemispherical grain (HSG) silicon lumps may be formed of doped polysilicon on the surface of a lower electrode, thereby increasing the effective area of the MIS capacitor. Specifically, polysilicon may be deposited on the surface of an amorphous silicon layer and may be heat-treated in a high vacuum. Silicon atoms around the surface of the amorphous silicon layer may move toward the surface of the polysilicon layer, and thus the HSG lumps may be formed.
The lower electrode of an MIM capacitor may be formed of noble metals, such as Au, Ag, Pd, Pt Ru, Ir, Rh, Hg or Os, and/or their conductive oxides. Since Ru, in particular, can be easily etched by plasma containing oxygen and can form conductive oxides, Ru often may be used in forming the lower electrode of a MIM capacitor. The lower electrode of a MIM capacitor may be formed to have a three-dimensional structure, such as a cylinder structure, a pin structure and/or a trench structure. However, an area increase effect induced by the formation of the HSG lumps in the MIS capacitor may not be obtained in the MIM structure because the lower electrode of the MIM structure is formed of metal rather than silicon.
Moreover, in order to obtain a high dielectric constant from the MIM capacitor, the dielectric layer may be crystallized after forming the dielectric layer and/or the MIM capacitor may be cured by heat-treating the MIM capacitor after forming the upper electrode. However, the dielectric layer may crack due to heat treatment. Thus, there may be limitations in the heat treatment, and the characteristics of a capacitor may be degraded due to the heat treatment.
SUMMARY OF THE INVENTION
Embodiments of the present invention provide integrated circuit MIM capacitors having a lower electrode that includes a metal layer on an integrated circuit substrate and hemispherical grain lumps that protrude from the metal layer. In some embodiments, the metal layer comprises a metal that is capable of inducing growth of crystal grains using a heat treatment. For example, in some embodiments, the metal layer comprises a noble metal. In other embodiments, the metal layer comprises at least one of the noble metals Pt, Ru, Rh, Ir, Os, and Pd. In some embodiments, the metal layer is heat-treated in a nitrogen atmosphere. The metal layer may be heat-treated at between about 500° C. to about 800° C. (for example, about 700° C.). In some embodiments, as a result of the heat treatment in a nitrogen atmosphere, crystal grains are grown on the surface of the metal layer, and the crystal grains form hemispherical grain lumps. Accordingly, in some embodiments, the metal layer and the hemispherical grain lumps both comprise at least one of Pt, Ru, Rh, Os, Ir, and Pd. In other embodiments, the metal layer and the hemispherical grain lumps both comprise the same material.
In other embodiments of the present invention, a metal layer is formed of an oxidizable metal. For example, the metal layer may comprise at least one of Ru, Rh, Os, and Pd. The metal layer is heat-treated in an oxygen atmosphere at about 500° C. As a result of the heat treatment in an oxygen atmosphere, hemispherical grain lumps are formed of a metal oxide on the surface of the metal layer. In some embodiments, before heat-treating the metal layer in an oxygen atmosphere, the metal layer is exposed to plasma containing O
2
gas, N
2
O gas, a mixed gas of He and O
2
, NO gas and/or a mixed gas of O
2
and N
2
so that the hemispherical grain lumps can be uniformly formed of the metal oxide.
According to other embodiments of the present invention, a lower electrode having hemispherical grain lumps includes a metal layer comprised of a first portion and a second portion. In these embodiments, the first and second portions of the metal layer comprise different metals. The hemispherical grain lumps protrude from the second portion of the metal layer. There may be no limitation in the material of the first portion. For example, the first portion may comprise TiN, Ti, or TaN which is used as a barrier layer. The second portion may be formed of a metal, which is capable of inducing growth of crystal grains using a heat treatment. For example, the second portion may comprise at least one of Pt, Ru, Rh, Os, Ir, and Pd. In some embodiments where the first portion is formed of a metal which is not readily oxidized, such as a Pt-based material, the second portion may be formed of an oxidizable metal. For example, the second portion may comprise at least one of Ru, Rh, Os, Ir, and Pd.
According to other embodiments of the present invention, a lower electrode having hemispherical grain lumps includes a metal layer comprised of a first portion and a second portion. In these embodiments, the first and second portions of the metal layer comprise different metals. The hemispherical grain lumps protrude from the second portion of the metal layer. In some embodiments, the surface of the first portion is treated such that the morphology of the surface of the first portion is retained during subsequent heat treatments that are performed after the formation of the first portion. The subsequent heat treatments may include a process for forming the hemispherical grain lumps to protrude from the second portion, a process for crystallizing a dielectric layer, and/or a process for curing a capacitor after forming an upper electrode.
Various embodiments of the present invention can retain the morphology of the first portion. In some embodiments, a metal layer used to form the first portion is formed on an integrated circuit substrate and then is exposed to plasma containing argon (Ar), oxygen (O
2
) and/or nitrogen (N
2
). In other embodiments, a metal layer used to form the first portion and a capping layer are sequentially formed on an integrated circuit substrate. Then, the metal layer covered with the capping layer is heat-treated in a nitrogen atmosphere at about 500° C. to about 800° C. (for example, about 700° C.), and the capping layer is removed. Next, the metal layer is exposed to plasma containing argon (Ar), oxygen (O
2
) and/or nitrogen (N
2
).
According to other embodiments of the present invention, a lower electrode having hemispherical grain lumps is formed by sequentially forming a metal layer and a metal oxide layer on an integrated circuit substrate and heat-treating the metal oxide layer in a nitrogen atmosphere. As a result of the heat treatment in a nitrogen atmosphere, the hemispherical grain lumps are formed to protrude from the metal oxide layer. In some embodiment
Joo Jae-hyun
Kim Wan-don
Park Soon-yeon
Won Seok-jun
Myers Bigel & Sibley & Sajovec
Picardat Kevin M.
Samsung Electronics Co,. Ltd.
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