Semiconductor device manufacturing: process – Electron emitter manufacture
Reexamination Certificate
1998-09-03
2001-12-04
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Electron emitter manufacture
C257S010000, C445S050000
Reexamination Certificate
active
06326221
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing field emitter arrays on a silicon-on-insulator (SOI) wafer by means of local oxidation of silicon (LOCOS) and for manufacturing field emitter arrays incorporated with MOSFETs (Metal Oxide Semi-conductor Feild Effect Transistors) on an SOI wafer.
The prior art to which the invention is related includes a method for manufacturing a low voltage driven field emitter array (the U.S. Pat. No. 5,651,713), which can make. gate hole patterns on a silicon substrate with the diameter of less than 0.5 &mgr;m and smaller than those formed by a photomask aligner by reducing the sizes of gate holes by LOCOS technique that has been used in the conventional semi-conductor manufacturing process.
The other prior arts are a method for manufacturing Si-FEAs (the U.S. Pat. No. 5,688,707) formed uniformly over a large area by etching polycrystalline or amorphous silicon layer deposited on an insulating substrate.
The former method for manufacturing a low voltage driven field emitter array provides a field emitter array on a silicon substrate with gate holes, the diameters of which are smaller than those formed by a photomask, reduced gate electrodes corresponding to the reduced gate holes and small metal field emitter tips suitable to the reduced gate electrodes, using a process for reducing the size of the gate holes during the gate insulating layer formation step.
According to the above method for manufacturing a low voltage driven field emitter array, a starting material may be a doped silicon substrate or a quartz substrate deposited thereon with a doped polycrystalline silicon or amorphous silicon. Further, according to the latter method for manufacturing Si-FEAs, silicon field emitter arrays can be formed uniformly over a large area with pixels insulated therebetween, using polycrystalline or amorphous silicon layer deposited on an insulating substrate as a starting material.
For using the metal field emitter array or Si-FEA made as above for a field emission display, each cathode line should be electrically isolated from others, through the junction isolation, which may makes the array liable to be unreliable and cause the manufacturing processes complex.
More particularly, a matrix panel of a field emission display has to be provided with isolated wells and gates crossing each other and electrons are emitted from microtips located on crossing points by an adequate voltage simultaneously applied between gates and wells functioning as cathodes and then accelerated toward the corresponding anode, thus producing light from the cathodoluminescent phosphor on the anode. Unfortunately, the steps for making well-to-well electrical isolation of the array for use in the above display have such problems as the above mentioned. The inventors have invented methods for manufacturing field emitter arrays in which electrical isolation between one cathode line and the other may be accomplished without junction isolation for solving the above problems.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a method for manufacturing field emitter arrays in which electrical isolation between one cathode line and the other is easily accomplished, the field emitter arrays made have minute gate holes and the corresponding minute gate electrodes and small metal field emitter tips are formed uniformly.
Another object of the present invention is to provide a method for manufacturing Si-FEAs in which electrical isolation between one cathode line and the other may be easily accomplished and the field emitter tips are formed uniformly over a large area.
Still another object of the present invention is to provide a method for manufacturing field emitter arrays incorporated with MOSFETs in which electrical isolation between one cathode line and the other is easily accomplished and field emitter arrays and MOSFETs for driving the field emitter arrays are formed on a single wafer, thereby achieving reduction of drive power and improvement on the quality of the FED.
According to an aspect of the present invention, using an SOI wafer as a staring substrate, metal field emitter arrays are manufactured by a process, comprising the steps of;
forming a doped silicon layer by doping a dopant on a single crystalline silicon layer of an SOI wafer;
making a buffer oxide layer on the doped silicon layer;
making a stripe pattern of silicon nitride on the buffer oxide layer;
etching the buffer oxide layer using the stripe pattern as a mask;
etching the doped silicon layer anisotropically using the stripe pattern as a mask;
making a minute mask pattern of silicon nitride on the buffer oxide layer by patterning the stripe pattern of silicon nitride;
selectively oxidizing the upper part of the doped silicon layer to form an oxide layer except on the portions under the mask pattern;
etching away the mask pattern of silicon nitride and the buffer oxide layer deposited under the mask pattern;
etching away the exposed doped silicon layer for making gate holes of undercut shape;
forming metal layers on the SOI wafer and the bottom of the gate holes by evaporating a metallic evaporant downwardly and vertically against the surface of the SOI wafer; and
forming the field emitter tips on the metal layer in the gate holes.
According to another aspect of the present invention, using an SOI wafer as a starting substrate, silicon field emitter arrays are manufactured by a process, comprising the steps of:
forming a doped silicon layer by doping a dopant on a single crystalline silicon layer of an SOI wafer;
making a minute oxide layer disk pattern on the doped silicon layer;
etching the doped silicon layer isotropically using the oxide layer disk pattern as a mask, for making field emitter tips;
forming hollows between the neighboring cathode lines for electrically insulating them from each other by etching the doped silicon layer;
forming a silicon oxide layer on the upper part of the doped silicon layer by means of a first oxidation thereof;
depositing a silicon nitride layer on the silicon oxide layer;
removing the silicon nitride layer except that of the sidewall parts around the field emitter tips;
forming a gate insulating layer by means of a second oxidation and removing the silicon nitride layer of the sidewall parts around the field emitter tips;
making contact windows by removing parts of the gate insulting layer for cathode contact with an external driving circuit;
depositing a metalic evaporant on the gate insulating layer and contact windows to form gate electrodes and cathode contacts;
etching away the silicon oxide layers around the field emitter tips and the metal deposited thereon; and
patterning the gate electrodes and cathode contacts.
Furthermore, according to the other aspect of the present invention, there is provided a method for manufacturing field emitter arrays incorporated with MOSFETs using an SOI wafer as a staring substrate by a process, comprising the steps of:
forming a first doped silicon layer and a second doped silicon layer with a predetermined interval by partially doping a dopant on a single crystalline silicon layer of an SOI wafer;
making a minute oxide disk pattern on the first doped silicon layer etching the doped silicon layers and the non-doped silicon layer isotropically using the oxide disk pattern as a mask for making field emitter tips;
forming a silicon oxide layer on the upper part of the doped silicon layers and the non-doped silicon layer by means of a first oxidation thereof;
deposting a silicon nitride layer on the silicon oxide layer;
removing the silicon nitride layer except that of sidewall parts around the field emitter tips by an anisotropical etching method;
coating photoresist layers on the first and second doped silicon layers, respectively;
performing boron doping on the portion between one photoresist layer and the other, thereby forming a doping channel;
removing the phothresist layers and forming a gate insulating layer on the doped silicon layers and the non-doped silicon layer
Lee Cheon Kyu
Lee Jong Duk
Uh Hyung Soo
Dilworth & Barrese LLP
Goodwin David
Jr. Carl Whitehead
Korean Information & Communication Co., Ltd.
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