Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates
Patent
1998-08-04
2000-07-25
Niebling, John F.
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
438459, H01L 2130
Patent
active
060936231
ABSTRACT:
Some advanced integrated circuits are fabricated as silicon-on-insulator structures, which facilitate faster operating speeds, closer component spacing, lower power consumption, and so forth. Unfortunately, current bonded-wafer techniques for making such structures are costly because they waste silicon. Accordingly, one embodiment of the invention provides a smart-bond technique that allows repeated use of a silicon wafer to produce hundreds and potentially thousands of silicon-on-insulator structures, not just one or two as do conventional methods. More precisely, the smart bond technique entails bonding selected first and second regions of a silicon substrate to an insulative substrate and then separating the two substrates to leave silicon protrusions or islands on the insulative substrate. The technique is also suitable to forming three-dimensional integrated circuits, that is, circuits having two or more circuit layers.
REFERENCES:
patent: 3407479 (1968-10-01), Fordemwalt et al.
patent: 3457123 (1969-07-01), Van Pul
patent: 3471754 (1969-10-01), Hoshi et al.
patent: 3689357 (1972-09-01), Jordan
patent: 4051354 (1977-09-01), Choate
patent: 4561932 (1985-12-01), Gris, et al.
patent: 4580331 (1986-04-01), Soclof
patent: 4604162 (1986-08-01), Sobczak
patent: 4625391 (1986-12-01), Sasaki
patent: 4663831 (1987-05-01), Birrittella et al.
patent: 4673962 (1987-06-01), Chatterjee et al.
patent: 4685198 (1987-08-01), Kawakita, et al.
patent: 4755481 (1988-07-01), Faraone
patent: 4761768 (1988-08-01), Turner et al.
patent: 4763183 (1988-08-01), Ng et al.
patent: 4766569 (1988-08-01), Turner et al.
patent: 4845048 (1989-07-01), Tamaki, et al.
patent: 4987089 (1991-01-01), Roberts
patent: 5001526 (1991-03-01), Gotou
patent: 5017504 (1991-05-01), Nishimura et al.
patent: 5021355 (1991-06-01), Dhong et al.
patent: 5028977 (1991-07-01), Kenneth et al.
patent: 5102817 (1992-04-01), Chatterjee et al.
patent: 5110752 (1992-05-01), Lu
patent: 5156987 (1992-10-01), Sandhu et al.
patent: 5177028 (1993-01-01), Manning
patent: 5202278 (1993-04-01), Mathews et al.
patent: 5208657 (1993-05-01), Chatterjee et al.
patent: 5223081 (1993-06-01), Doan
patent: 5234535 (1993-08-01), Beyer et al.
patent: 5266514 (1993-11-01), Tuan et al.
patent: 5320880 (1994-06-01), Sandhu et al.
patent: 5327380 (1994-07-01), Kersh, III et al.
patent: 5376575 (1994-12-01), Kim et al.
patent: 5391911 (1995-02-01), Beyer et al.
patent: 5392245 (1995-02-01), Manning
patent: 5393704 (1995-02-01), Huang et al.
patent: 5396093 (1995-03-01), Lu
patent: 5410169 (1995-04-01), Yamamoto et al.
patent: 5414287 (1995-05-01), Hong
patent: 5416041 (1995-05-01), Schwalke
patent: 5422499 (1995-06-01), Manning
patent: 5426070 (1995-06-01), Shaw et al.
patent: 5438009 (1995-08-01), Yang et al.
patent: 5440158 (1995-08-01), Sung-Mu
patent: 5441591 (1995-08-01), Imthurn et al.
patent: 5445986 (1995-08-01), Hirota
patent: 5460316 (1995-10-01), Hefele
patent: 5460988 (1995-10-01), Hong
patent: 5466625 (1995-11-01), Hsieh et al.
patent: 5483094 (1996-01-01), Sharma et al.
patent: 5483487 (1996-01-01), Sung-Mu
patent: 5492853 (1996-02-01), Jeng et al.
patent: 5495441 (1996-02-01), Hong
patent: 5497017 (1996-03-01), Gonzales
patent: 5504357 (1996-04-01), Kim et al.
patent: 5508219 (1996-04-01), Bronner et al.
patent: 5508542 (1996-04-01), Geiss et al.
patent: 5528062 (1996-06-01), Hsieh et al.
patent: 5593912 (1997-01-01), Rajeevakumar
patent: 5616934 (1997-04-01), Dennison et al.
patent: 5640342 (1997-06-01), Gonzalez
patent: 5644540 (1997-07-01), Manning
patent: 5646900 (1997-07-01), Tsukude et al.
patent: 5691230 (1997-11-01), Forbes
patent: 5710057 (1998-01-01), Kenney
patent: 5773152 (1998-06-01), Okonogi
Eaton, W.P., et al., "Wafer Bonding by Low Temperature Melting Glass", Proceedings of the First International Symposium on Semiconductor Wafer Bonding, Gosele, U., et al., (eds.), Electrochemical Society, Pennington, NJ, 146-152, (1992).
Horiuchi, M., et al., "A Mechanism of Silicon Wafer Bonding", Proceedings of the First International Symposium on Semiconductor Wafer Bonding, Gosele, U., et al., (eds.), Electrochemical Society, Pennington, NJ, 48-61, (1992).
Quenzer, H.J., et al., "Low Temperature Silicon Wafer Bonding for Micromechanical Applications", Proceedings of the First International Symposium on Semiconductor Wafer Bonding, Gosele, U., et al., (eds.), Electrochemical Society, Pennington, NJ, 92-100, (1992).
"Proceedings of the 1st, 2nd, and 3rd International Symposia on Semiconductor Wafer Bonding: Science, Technology and Applications", The Electrochemical Society Proceedings Series, Electrochemical Society, Pennington, NJ (1992 Issue), 48-62, 92-100, 146-152, (1992-1995).
Abe, et al., "Silicon Wafer-Bonding Process Technology for SOI Structures", Conference on Solid State Devices and Materials, Sponsored by The Japan Society of Applied Physics, 853-856, (1990).
Adler, E., et al., "The Evolution of IBM CMOS DRAM Technology", v, 167-188, (Jan./Mar., 1995).
Asai, S., et al., "Technology Challenges for Integration Near and Below 0.1 micrometer", Proceedings of the IEEE, 85, Special Issue on Nanometer-Scale Science & Technology, 505-520, (Apr. 1997).
Auberton-Herve, A.J., "SOI: Materials to Systems", Digest of the International Electron Device Meeting, San Francisco, 5-10, (Dec. 1996).
Banerjee, S.K., et al., "Characterization of Trench Transistors for 3-D Memories", 1986 Symposium on VLSI Technology, Digest of Technical Papers, San Diego, CA, 79-80, (May 28-30, 1986).
Blalock, T.N., et al., "A High-Speed Sensing Scheme for 1T Dynamic RAM's Utilizing the Clamped Bit-Line Sense Amplifier", IEEE Journal of Solid-State Circuits, 27, 618-625, (Apr. 1992).
Bomchil, G., et al., "Porous Silicon: The Material and its Applications in Silicon-On-Insulator Technologies", Applied Surface Science, 41/42, 604-613, (1989).
Burnett, D., et al., "Implications of Fundamental Threshold Voltage Variations for High-Density SRAM and Logic Circuits", 1994 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI 15-16, (Jun. 4-7, 1994).
Burnett, D., et al., "Statistical Threshold-Voltage Variation and its Impact on Supply-Voltage Scaling", Proceedings SPIE: Microelectronic Device and Multilevel Interconnection Technology, 2636, 83-90, (1995).
Chen, M.J., et al., "Back-Gate Forward Bias Method for Low-Voltage CMOS Digital Circuits", IEEE Transactions on Electron Devices, 43, 904-909, (Jun. 1986).
Chen, M.J., et al., "Optimizing the Match in Weakly Inverted MOSFET's by Gated Lateral Bipolar Action", IEEE Transactions on Electron Devices, 43, 766-773, (May 1996).
Chesler, R., et al., "Solid-State Ionic Lasers", Laser Handbook, North-Holland Publishing Company, edited by F.T. Arrechi and E.O. Schulz-Dubois, 353, (1972).
Chung, I.Y., et al., "A New SOI Inverter for Low Power Applications", Proceedings of the 1996 IEEE International SOI Conference, Sanibel Island, FL, 20-21, (Sep. 30-Oct. 3, 1996).
De, V.K., et al., "Random MOSFET Parameter Fluctuation Limits to Gigascale Integration (GSI)", 1996 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, 198-199, (Jun. 11-13, 1996).
Denton, J.P., et al., "Fully Depleted Dual-Gated Thin-Film SOI P-MOSFET's Fabricated in SOI Islands with an Isolated Buried Polysilicon Backgate", IEEE Electron Device Letters, 17, 509-511, (Nov. 1996).
Fong, Y., et al., "Oxides Grown on Textured Single-Crystal Silicon-Dependence on Process and Application in EEPROMs", IEEE Transactions on Electron Devices, 37, 583-590, (Mar. 1990).
Forbes, L., et al., "Resonant Forward-Biased Guard-Ring Diodes for Suppression of Substrate Noise in Mixed-Mode CMOS Circuits", Electronics Letters, 31, 720-721, (Apr. 1995).
Foster, R., et al., "High Rate Low-Temperature Selective Tungsten", In: Tungsten and Other Refractory Metals for VLSI Applications III, V.A. Wells, ed., Materials Res. Soc., Pittsburgh, PA, 69-72, (1988).
Fuse, T., et al., "A 0.5V 200MHz 1-Stage 32b ALU Using a Body Bias Controlled SOI Pass-Gate Logic", 1997 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 286-287, (1997).
Gag
Drake Eduardo E.
Lindsay Jr. Walter L.
Micro)n Technology, Inc.
Niebling John F.
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