Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – Groove
Reexamination Certificate
1998-12-31
2002-03-19
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
Groove
C257S774000, C257S758000
Reexamination Certificate
active
06359328
ABSTRACT:
TECHNICAL FIELD
The present invention concerns methods of fabricating integrated circuits, particularly methods of making integrated-circuit wiring, or interconnects, from metal and method of inhibiting metal diffusion through insulation.
BACKGROUND OF THE INVENTION
Integrated circuits, the key components in thousands of electronic and computer products, are interconnected networks of electrical components fabricated on a common foundation, or substrate. Fabricators typically use various techniques, such as layering, doping, masking, and etching, to build thousands and even millions of microscopic resistors, transistors, and other electrical components on a silicon substrate, known as a wafer. The components are then wired, or interconnected, together to define a specific electric circuit, such as a computer processor.
To interconnect millions of microscopic components, fabricators sometimes use a dual-damascene metallization technique, which takes its name from the ancient Damascan metalworking art of inlaying metal in grooves or channels to form ornamental patterns. The dual-damascene technique entails covering the components with an insulative layer, etching small holes in the insulative layer to expose portions of the components underneath, and etching shallow trenches from hole to hole to define a wiring pattern. Fabricators then execute a single deposition procedure, such as chemical or physical vapor deposition, to blanket the entire insulative layer with a thin sheet of aluminum. Some of this aluminum fills the holes and trenches and the rest lies on the higher surfaces of the insulative layer. The aluminum on these higher surfaces is then polished or scraped off, leaving behind aluminum vias, or contact plugs, in the holes and thin aluminum wires in the trenches. The wires are typically about one micron thick, or about 100 times thinner than a human hair.
This dual-damascene technique suffers from at least two problems. The first problem is that it uses a single-deposition procedure, which works fairly well for depositing aluminum into wide and shallow holes and trenches, but it is much less effective for narrow and deep ones, particularly those having width-to-depth, or aspect, ratios greater than five. For these aspect ratios, the single-deposition procedure using chemical or physical vapor deposition yields contact plugs and wires that have voids or cavities dispersed throughout and thus increased electrical resistance. Increased electrical resistance wastes power and slows down the transfer of electrical signals through an integrated circuit.
Fabricators have tried to solve this cavity problem, particularly for copper, using “reflow” techniques which entail depositing copper using standard cavity-prone methods and then heating the copper near its melting point. Melting the copper causes it to consolidate and thus eliminates cavities. (See S. Hirao et al, “A Novel Copper Reflow Process Using Dual Wetting Layers,” Symposium on VLSI Technology, Digest of Technical Papers, pp. 57-58 (1997)). However, these “reflow” techniques preclude the use of certain materials having melting points lower than that of the deposited metal. This is particularly true for some low-melting-point insulators which would improve integrated-circuit speed and efficiency.
The second problem with the conventional dual-damascene technique is its incompatibility with metals, such as gold, silver, and copper. These metals are more desirable than aluminum because their lower electrical resistance enhances efficiency and speed of integrated circuits and their higher electromigration resistance offers superior reliability. The incompatibility stems from how easy these metals diffuse through silicon-dioxide insulation and thus form short circuits with neighboring wires. Although the diffusion can be prevented by cladding the contact plugs and wires in diffusion barriers, conventional dual-damascene techniques require extra deposition steps to form the barriers. These extra depositions are not only time-consuming but also increase the cost of fabrication.
Accordingly, there is a need for better methods of making contact plugs and wiring, especially methods of making high-aspect-ratio contact plugs and wiring from metals, such as gold, silver, and copper, and more efficient methods of making diffusion barriers.
SUMMARY OF THE INVENTION
To address these and other needs, the inventor devised a new dual-damascene method and a new method of making diffusion barriers for gold, silver, copper, and other metals. Specifically, one embodiment of the new dual-damascene method divides the single-deposition step of conventional dual-damascene techniques into two depositions: a selective electroless deposition for forming vias, or contact plugs with fewer voids, and a conventional deposition process, such as chemical or physical vapor deposition, to fill trenches. Other embodiments fill the trenches using an electroless deposition after forming barrier or seed layers in the trenches using chemical or physical vapor deposition.
One embodiment of the new method of making diffusion barriers entails adding a surfactant to a metal, depositing the metal on an insulative structure, and then removing at least some of the surfactant to form a gap, which serves as a diffusion barrier, between the de ited metal and the insulative structure. Another embodiment of this method leaves the surfactant in place to serve as a diffusion barrier.
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Clark Sheila V.
Drake Eduardo E.
Intel Corporation
Schwegman Lundberg Woessner & Kluth P.A.
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