Methods for improving radiation tolerance of silicon gate CMOS/s

Details Methods for improving radiation tolerance of silicon gate CMOS/s Methods for improving radiation tolerance of silicon gate CMOS/s

1990-02-27

1991-04-09

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 67, 437 57, 437 27, 437 84, 148DIG150, 148DIG131, H01L 21266, H01L 21223, H01L 21336

Patent

active

050064797

ABSTRACT:
The radiation hardened NFET and process of the subject Methods and Structures for Improving Radiation Tolerance of Silicon Gate CMOS/Silicon on Sapphire Devices utilizes boron edge doping of a silicon epi island on sapphire at the island opposed edges in the region which will be the P-doped region of the finished transistor. Multiple boron ion implants are made into the silicon adjacent to the active region and driven-in to provide a uniform edge doping. Alternatively, a furnace containing a source of boron vapor and the sapphire wafer is used to dope the island edges at high temperatures.

REFERENCES:
patent: 4070211 (1978-01-01), Harari
patent: 4160260 (1979-07-01), Weitzel et al.
patent: 4753896 (1988-06-01), Matloubian
Wolf, S., Silicon Processing for the VSLI Era, vol. 1, Lattice Press, 1986, pp. 264-265, 280-327.
Capell, A. et al., "Process Refinements . . . ", Electronics, May 26, 1977, pp. 99-105.

Affiliated with

Also associated with

Rating

Methods for improving radiation tolerance of silicon gate CMOS/s does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods for improving radiation tolerance of silicon gate CMOS/s, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods for improving radiation tolerance of silicon gate CMOS/s will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2034260