Methods for growing defect-free heteroepitaxial layers

Details Methods for growing defect-free heteroepitaxial layers Methods for growing defect-free heteroepitaxial layers

1998-10-06

2001-02-06

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C117S001000, C117S954000

Reexamination Certificate

active

06184144

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to methods for growing high-quality, defect-free heteroepitaxial layers on any crystal substrates, regardless of the degree of lattice mismatch between the layers and the substrates.
A long-sought dream for semiconductor material research is to find methods for growing high-quality epitaxial layers on essentially any substrates regardless of the degree of lattice mismatch. However, the analysis of strain energy in a pseudomorphic material system suggests that this dream is unlikely to come true because threading dislocations will form when the epilayer thickness is well above the critical thickness. The concept of critical thickness has been so widely accepted by the semiconductor community that it has been used as a guiding principle for design of compound semiconductor material systems.
Recently, the emergence of compliant substrates raised hopes of lifting the constraint of critical thickness. By making the substrate compliant to an epitaxial layer grown on top, it is theoretically possible to grow threading dislocation free heteroepitaxy. One promising compliant substrate technology developed by the inventor involves bonding an ultra-thin semiconductor layer to a bulk crystal with an angle between their crystal axes, thereby forming a so-called twist-bonded compliant substrate. Experimental results have shown that threading dislocation free InGaP, InGaAs and InSb layers can be grown on such twist-bonded GaAs compliant substrates with a lattice mismatch as large as 15% in some cases. Other compliant substrates may have an SOI structure or use other thin film and bulk crystal bonding techniques.
In spite of the encouraging initial results obtained from compliant substrates, putting very thin (say 100 Å) single crystal semiconductor layers on a bulk crystal is a very challenging and sometimes costly task. For low cost devices such as color LEDs, solar cells and solid state sensors, substrate cost becomes a significant part of the device cost. In such situations, the compliant substrate approach will have to face a trade-off between the device cost and performance. Thus, the most ideal scenario would be if high-quality heteroepitaxial layers could be formed on any commercial semiconductor substrates, such as Si and GaAs substrates, without having to perform any pre-growth processing or treatment of the substrates.
SUMMARY OF THE INVENTION
The present invention addresses the foregoing concerns by providing two new methods for growing defect-free heteroepitaxial layers on any type of substrates, including conventional semiconductor substrates, which do not require special pre-growth treatment of the substrates. In the new methods, instead of making special treatments of the substrate surface as is done for compliant substrates, the nature of the material growth is employed to achieve defect-free heteroepitaxy. More particularly, specific growth steps are employed which inherently eliminate either the defects or the stresses which cause the defects.
Both of the methods rely on the formation of small three-dimensional islands on the substrate, which are subsequently exposed to treatment steps that cause the islands to coalesce, and form a smooth, defect-free surface. In a first of the methods, the following specific steps are carried out: initializing three-dimensional island growth, facilitating strain relaxation by thermal annealing, removing harmful defects using in-situ etching which leaves the benign defects at the heteroepitaxial interface intact, creating island coalescence, and starting two-dimensional growth to achieve a smooth surface. When islands are nucleated on the substrate surface, the islands may contain no defects even with a large lattice mismatch until they reach a certain size. When the islands become larger, the second step, thermal annealing, will result in defect generation within each island so that its internal strain can be relaxed. The interfacial misfit dislocations are considered the “benign defects” since they always stay at the interface; but the segments of defects near the edges of the island tend to propagate towards the surface as harmful threading dislocations. Unfortunately, these “harmful” defects always coexist with the “benign” defects since together they form a stable dislocation half loop. The third step is to remove only the “harmful” dislocation sections by in-situ etching. This is possible since all “harmful” dislocations are located very near the edges of the islands so etching of only a few monolayers of the heteroepitaxial material can remove those defects completely.
After repeating the above steps a few times, the islands grow bigger after each cycle while remaining strain relaxed and free of “harmful” dislocations. Finally, these islands will coalesce. The coalescence of islands creates additional strain to the heteroepitaxial layer since the spacing between two islands is not necessarily multiples of the equilibrium lattice spacing of the heteroepitaxial material. However, it can be shown, that the additional strain is first of all, too small to create new “harmful” defects and secondly, will not be accumulated to form long range strain when all islands coalesce to form a continuous layer. It can be proved that the net strain due to coalescence of all the islands should vanish due to the cancellation of strain of different polarities. Once a continuous and lattice-relaxed heteroepitaxial layer is formed, the surface will be smoothed by further growth to reduce the surface energy of the material. This will finally lead to a high-quality heteroepitaxial layer with a featureless surface morphology, most ideal for device applications.
In the second method, the islands, otherwise referred to as patches, are each no bigger than a few hundred nanometers in diameter, and are formed from a single crystal. The patches serve as nucleation sites for growth of single crystal heteroepitaxial layers. Because of the very small patch size, the stress (normal stress and shear stress) due to lattice mismatch will be reduced significantly. As the growth proceeds, the size of nucleation islands increases in both vertical and lateral directions and the discrete islands soon coalesce to form a continuous thin film. It is critical that no dislocations are generated at the conjunction of islands. If all coalescing islands have the same or nearly the same crystal orientation, then the net stress will be close to zero. This means that the smooth, defect-free heteroepitaxial layer can be grown to any thickness without a critical thickness limit.


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