Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1999-06-11
2004-09-28
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S649000, C438S663000, C438S655000, C438S659000, C438S763000
Reexamination Certificate
active
06797601
ABSTRACT:
TECHNICAL FIELD
The invention pertains to a number of semiconductor structures and methods for forming such structures, including gate stack structures, conductive line structures, conductive interconnect structures, and programmable-read-only-memory devices.
BACKGROUND OF THE INVENTION
A continuous challenge in semiconductor processing is to improve conductivity and performance of stacked semiconductor structures. Among the stacked semiconductor structures commonly utilized are gate stacks, wordlines, programmable-read-only-memory devices such as EPROMs and EEPROMs, and conductive interconnects. Formation of some of these prior art stacked structures is described with reference to
FIGS. 1-4
.
FIGS. 1-2
pertain to the formation of a wordline or gate stack structure, and
FIGS. 3-4
pertain to the formation of a programmable-read-only memory device.
Referring to
FIG. 1
, a semiconductor wafer fragment
10
is illustrated at a preliminary processing step of a prior art process for forming a wordline or gate stack. Wafer fragment
10
comprises a semiconductive material substrate
12
, and field oxide regions
14
over substrate
12
. A gate dielectric layer
16
, generally comprising silicon dioxide, extends between field oxide regions
14
. A polysilicon layer
18
and a polycide (silicide) layer
20
are formed over field oxide regions
14
and gate dielectric layer
16
.
Polysilicon layer
18
typically comprises polysilicon uniformly doped with a conductivity enhancing dopant (illustrated by stippling within layer
18
). Polycide layer
20
comprises a metal silicide, such as tungsten silicide, molybdenum silicide, titanium silicide or cobalt silicide. The formation of polycide layer
20
typically comprises depositing a metal over polysilicon layer
18
and reacting the metal with polysilicon layer
18
to form a metal-silicide. The reacting can comprise thermal processing of the metal layer and polysilicon layer at, for example, temperatures of from about 600° C. to about 800° C.
Referring to
FIG. 2
, layers
16
,
18
and
20
are patterned to form a conductive stack, and specifically to form a wordline
24
. Source/drain regions
25
are provided proximate wordline
24
. Conductive wordline
24
comprises a transistor gate electrically connecting source/drain regions
25
. The final transistor structure can be either a p-channel transistor (PMOS), or an n-channel transistor (NMOS), and can be incorporated within a CMOS construction.
The speed of devices comprising wordlines and conductive gates generally increases with increasing conductivities of the wordlines and conductive gates. Accordingly, it would be desirable to improve the conductivity of wordlines and transistor gates. A method for improving the conductivity of a doped layer is to “activate” the dopant within the layer. Although the chemistry of dopant activation is not well understood, activation is thought to occur as dopant is dispersed from grain boundaries in a polysilicon layer to bulk polysilicon away from the grain boundaries. Dopants are typically activated by thermal processing.
Alternative procedures similar to those of
FIGS. 1 and 2
can be used to form a conductive polysilicon interconnect. Such interconnects can comprise a line of polycide over a polysilicon. Accordingly, such interconnects are similar to wordline
24
, but lack dielectric layer
16
.
The speed of devices comprising conductive interconnects can increase with increasing conductivities of the conductive interconnects. Accordingly, it would be desirable to improve the conductivity of conductive interconnects.
Referring to
FIGS. 3-4
, a prior art process for forming a programmable-read-only memory (PROM) device is illustrated. In the embodiment of
FIGS. 3-4
, similar numbering to that of the embodiment of
FIGS. 1-2
is utilized, with differences indicated by the suffix “a”, or by different numbers.
Referring to
FIG. 3
, a wafer fragment
10
a
is illustrated at a preliminary step during formation of a programmable-read-only memory device. Wafer fragment
10
a
comprises a semiconductive material
12
a
over which is formed field oxide regions
14
a
and gate dielectric layer
16
a
. A first polysilicon layer
18
a
is formed over regions
14
a
and dielectric layer
16
a
. A second dielectric layer
26
and a second polysilicon layer
28
are formed over first polysilicon layer
18
a
, and a polycide layer
30
is formed over second dielectric layer
26
.
Polysilicon layers
18
a
and
28
comprise uniformly doped polysilicon, typically comprising a dopant concentration of greater than 1×10
19
ions/cm
3
.
Referring to
FIG. 4
, layers
16
a
,
18
a
,
20
a
,
26
,
28
and
30
are patterned to form the resulting PROM device
32
. Within device
32
, the patterned first polysilicon layer
18
a
is typically referred to as a floating gate. The patterned second polysilicon layer
28
and polycide layer
30
together comprise a conductive line
33
.
The speed of circuits comprising PROM devices can increase with increasing conductivities of the conductive line and floating gate. Accordingly, it would be desirable to improve the conductivities of conductive lines and floating gates.
SUMMARY OF THE INVENTION
The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures.
In one aspect, the invention includes a method of forming a conductive line. A silicide layer is formed against a polysilicon layer. A conductivity-enhancing impurity is provided within the silicide layer. The polysilicon layer and the silicide layer are formed into a conductive line shape.
In another aspect, the invention includes a programmable-read-only-memory device comprising a first dielectric layer over a substrate, a floating gate over the first dielectric layer, a second dielectric layer over the floating gate, a conductive line over the second dielectric layer, and a metal-silicide layer over the conductive line. The metal-silicide layer comprises a Group III dopant or a Group V dopant.
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Schuegraf Klaus Florian
Thakur Randhir P. S.
John P.S. Wells St.
Pompey Ron
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