Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Diffusing a dopant
Reexamination Certificate
1999-06-15
2004-05-04
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Diffusing a dopant
C438S491000, C438S530000, C438S532000, C438S653000, C438S654000
Reexamination Certificate
active
06730584
ABSTRACT:
TECHNICAL FIELD
The invention pertains to a number of semiconductor structures and methods for forming such structures, including gate stack structures, conductive line structures, conductive interconnect structures, and programmable-read-only-memory devices.
BACKGROUND OF THE INVENTION
A continuous challenge in semiconductor processing is to improve conductivity and performance of stacked semiconductor structures. Among the stacked semiconductor structures commonly utilized are gate stacks, wordlines, programmable-read-only-memory devices such as EPROMs and EEPROMs, and conductive interconnects. Formation of some of these prior art stacked structures is described with reference to
FIGS. 1-4
.
FIGS. 1-2
pertain to the formation of a wordline or gate stack structure, and
FIGS. 3-4
pertain to the formation of a programmable-read-only memory device.
Referring to
FIG. 1
, a semiconductor wafer fragment
10
is illustrated at a preliminary processing step of a prior art process for forming a wordline or gate stack. Wafer fragment
10
comprises a semiconductive material substrate
12
, and field oxide regions
14
over substrate
12
. A gate dielectric layer
16
, generally comprising silicon dioxide, extends between field oxide regions
14
. A polysilicon layer
18
and a polycide (silicide) layer
20
are formed over field oxide regions
14
and gate dielectric layer
16
.
Polysilicon layer
18
typically comprises polysilicon uniformly doped with a conductivity enhancing dopant (illustrated by stippling within layer
18
). Polycide layer
20
comprises a metal silicide, such as tungsten silicide, molybdenum silicide, titanium silicide or cobalt silicide. The formation of polycide layer
20
typically comprises depositing a metal over polysilicon layer
18
and reacting the metal with polysilicon layer
18
to form a metal-silicide. The reacting can comprise thermal processing of the metal layer and polysilicon layer at, for example, temperatures of from about 600° C. to about 800° C.
Referring to
FIG. 2
, layers
16
,
18
and
20
are patterned to form a conductive stack, and specifically to form a wordline
24
. Source/drain regions
25
are provided proximate wordline
24
. Conductive wordline
24
comprises a transistor gate electrically connecting source/drain regions
25
. The final transistor structure can be either a p-channel transistor (PMOS), or an n-channel transistor (NMOS), and can be incorporated within a CMOS construction.
The speed of devices comprising wordlines and conductive gates generally increases with increasing conductivities of the wordlines and conductive gates. Accordingly, it would be desirable to improve the conductivity of wordlines and transistor gates. A method for improving the conductivity of a doped layer is to “activate” the dopant within the layer. Although the chemistry of dopant activation is not well understood, activation is thought to occur as dopant is dispersed from grain boundaries in a polysilicon layer to bulk polysilicon away from the grain boundaries. Dopants are typically activated by thermal processing.
Alternative procedures similar to those of
FIGS. 1 and 2
can be used to form a conductive polysilicon interconnect. Such interconnects can comprise a line of polycide over a polysilicon. Accordingly, such interconnects are similar to wordline
24
, but lack dielectric layer
16
.
The speed of devices comprising conductive interconnects can increase with increasing conductivities of the conductive interconnects. Accordingly, it would be desirable to improve the conductivity of conductive interconnects.
Referring to
FIGS. 3-4
, a prior art process for forming a programmable-read-only memory (PROM) device is illustrated. In the embodiment of
FIGS. 3-4
, similar numbering to that of the embodiment of
FIGS. 1-2
is utilized, with differences indicated by the suffix “a”, or by different numbers.
Referring to
FIG. 3
, a wafer fragment
10
a
is illustrated at a preliminary step during formation of a programmable-read-only memory device. Wafer fragment
10
a
comprises a semiconductive material
12
a
over which is formed field oxide regions
14
a
and gate dielectric layer
16
a
. A first polysilicon layer
18
a
is formed over regions
14
a
and dielectric layer
16
a
. A second dielectric layer
26
and a second polysilicon layer
28
are formed over first polysilicon layer
18
a
, and a polycide layer
30
is formed over second dielectric layer
26
.
Polysilicon layers
18
a
and
28
comprise uniformly doped polysilicon, typically comprising a dopant concentration of greater than 1×10
19
ions/cm
3
.
Referring to
FIG. 4
, layers
16
a
,
18
a
,
20
a
,
26
,
28
and
30
are patterned to form the resulting PROM device
32
. Within device
32
, the patterned first polysilicon layer
18
a
is typically referred to as a floating gate. The patterned second polysilicon layer
28
and polycide layer
30
together comprise a conductive line
33
.
The speed of circuits comprising PROM devices can increase with increasing conductivities of the conductive line and floating gate. Accordingly, it would be desirable to improve the conductivities of conductive lines and floating gates.
SUMMARY OF THE INVENTION
The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures.
The invention includes a method of forming a transistor gate. A gate dielectric layer is formed and a polysilicon gate layer is formed against the gate dielectric layer. The polysilicon gate layer is doped with a conductivity-enhancing dopant. The dopant is provided in a concentration gradient within the polysilicon layer which increases in a direction toward the gate dielectric layer.
The invention also includes a wordline comprising a polysilicon line, a substantially fluorine impervious barrier layer over the polysilicon line, and a layer of metal-silicide over the substantially fluorine impervious barrier layer.
REFERENCES:
patent: 4354309 (1982-10-01), Gardiner et al.
patent: 4559091 (1985-12-01), Allen et al.
patent: 4700215 (1987-10-01), McPherson
patent: 4833099 (1989-05-01), Woo
patent: 4886765 (1989-12-01), Chen et al.
patent: 5047831 (1991-09-01), Katayama
patent: 5053351 (1991-10-01), Fazan et al.
patent: 5093700 (1992-03-01), Sakata
patent: 5164333 (1992-11-01), Schwalke et al.
patent: 5192708 (1993-03-01), Beyer et al.
patent: 5208182 (1993-05-01), Narayan et al.
patent: 5256894 (1993-10-01), Shino
patent: 5350698 (1994-09-01), Huang et al.
patent: 5355010 (1994-10-01), Fujii et al.
patent: 5364803 (1994-11-01), Lur et al.
patent: 5393676 (1995-02-01), Anjum et al.
patent: 5393685 (1995-02-01), Yoo et al.
patent: 5425392 (1995-06-01), Thakur et al.
patent: 5439833 (1995-08-01), Hebert et al.
patent: 5441904 (1995-08-01), Kim et al.
patent: 5472896 (1995-12-01), Chen et al.
patent: 5481128 (1996-01-01), Hong
patent: 5650648 (1997-07-01), Kapoor
patent: 5652156 (1997-07-01), Liao et al.
patent: 5710454 (1998-01-01), Wu
patent: 5712181 (1998-01-01), Byun et al.
patent: 5723893 (1998-03-01), Yu et al.
patent: 5741725 (1998-04-01), Inoue et al.
patent: 5767004 (1998-06-01), Balasubramanian et al.
patent: 5767558 (1998-06-01), Lo et al.
patent: 5798296 (1998-08-01), Fazan et al.
patent: 5811343 (1998-09-01), Wann et al.
patent: 5818092 (1998-10-01), Bai et al.
patent: 5840607 (1998-11-01), Yeh et al.
patent: 5861340 (1999-01-01), Bai et al.
patent: 5877074 (1999-03-01), Jeng et al.
patent: 5915197 (1999-06-01), Yamanaka et al.
patent: 5930655 (1999-07-01), Cooney, III et al.
patent: 5985720 (1999-11-01), Saitoh
patent: 5986312 (1999-11-01), Kuroda
patent: 6040238 (2000-03-01), Yang et al.
patent: 6060741 (2000-05-01), Huang
patent: 6066577 (2000-05-01), Cooney, III et al.
patent: 6130145 (2000-10-01), Ilg et al.
patent: 6208004 (2001-03-01), Cunningham
patent: 6214730 (2001-04-01), Cooney, III et al.
patent: 6239458 (2001-05-01), Liaw et al.
patent: 6262458 (2001-07-01), Hu
patent: 6310300 (2001-10-01), Cooney, III et al.
patent: 2265248 (
Powell Carl
Schuegraf Klaus Florian
Thakur Randhir P. S.
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